3 V, LVDS, Quad, CMOS
Differential Line Driver
ADN4665
FUNCTIONAL BLOCK DIAGRAM
FEATURES
15 kV ESD protection on output pins
400 Mbps (200 MHz) switching rates
100 ps typical differential skew
V
CC
ADN4665
D
D
IN4
IN1
D4
D1
400 ps maximum differential skew
2 ns maximum propagation delay
3.3 V power supply
D
D
D
OUT4+
OUT1+
D
OUT1–
OUT4–
350 mV differential signaling
EN
EN
D
Low power dissipation (13 mW typical)
Interoperable with existing 5 V LVDS receivers
High impedance on LVDS outputs on power-down
Conforms to TIA/EIA-644 LVDS standards
Industrial operating temperature range: −40°C to +85°C
Available in surface-mount SOIC package and low profile
TSSOP package
D
D
OUT3–
OUT2–
D
OUT3+
OUT2+
D3
D2
D
D
IN2
IN3
GND
APPLICATIONS
Figure 1.
Backplane data transmission
Cable data transmission
Clock distribution
GENERAL DESCRIPTION
The ADN4665 is a quad-channel, CMOS, low voltage differential
signaling (LVDS) line driver offering data rates of over 400 Mbps
(200 MHz) and ultralow power consumption.
The ADN4665 also offers active high and active low enable/
EN
disable inputs (EN and ). These inputs control all four drivers
and turn off the current outputs in the disabled state to reduce
the quiescent power consumption to typically 10 mW.
The device accepts low voltage TTL/CMOS logic signals and
converts them to a differential current output of typically ±±.5 mA
for driving a transmission medium such as a twisted pair cable.
The transmitted signal develops a differential voltage of typi-
cally ±±50 mV across a termination resistor at the receiving end.
This voltage is converted back to a TTL/CMOS logic level by an
LVDS receiver.
The ADN4665 offers a new solution to high speed, point-to-point
data transmission and offers a low power alternative to emitter-
coupled logic (ECL) or positive emitter-coupled logic (PECL).
Rev. 0
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