Datasheet > 驱动程序和接口 > 线路驱动器或接收器> ADN4665ARZ

ADN4665ARZ

更新时间： 2024-01-21 00:49:37

品牌	Logo	应用领域
亚德诺 - ADI		线路驱动器或接收器驱动程序和接口接口集成电路光电二极管 PC
页数	文件大小	规格书
12页	252K
描述
3 V, LVDS, Quad, CMOS Differential Line Driver

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ADN4665ARZ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	ROHS COMPLIANT, MS-012AC, SOIC-16	针数：	16
Reach Compliance Code：	unknown	风险等级：	5.48
差分输出：	YES	驱动器位数：	4
输入特性：	STANDARD	接口集成电路类型：	LINE DRIVER
接口标准：	EIA-644; TIA-644	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	9.9 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	225
座面最大高度：	1.75 mm	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
最大传输延迟：	2 ns	宽度：	3.9 mm
Base Number Matches：	1

ADN4665ARZ 数据手册

3 V, LVDS, Quad, CMOS

Differential Line Driver

ADN4665

FUNCTIONAL BLOCK DIAGRAM

FEATURES

15 kV ESD protection on output pins

400 Mbps (200 MHz) switching rates

100 ps typical differential skew

ADN4665

IN4

IN1

400 ps maximum differential skew

2 ns maximum propagation delay

3.3 V power supply

OUT4+

OUT1+

OUT1–

OUT4–

350 mV differential signaling

Low power dissipation (13 mW typical)

Interoperable with existing 5 V LVDS receivers

High impedance on LVDS outputs on power-down

Conforms to TIA/EIA-644 LVDS standards

Industrial operating temperature range: −40°C to +85°C

Available in surface-mount SOIC package and low profile

TSSOP package

OUT3–

OUT2–

OUT3+

OUT2+

IN2

IN3

GND

APPLICATIONS

Figure 1.

Backplane data transmission

Cable data transmission

Clock distribution

GENERAL DESCRIPTION

The ADN4665 is a quad-channel, CMOS, low voltage differential

signaling (LVDS) line driver offering data rates of over 400 Mbps

(200 MHz) and ultralow power consumption.

The ADN4665 also offers active high and active low enable/

disable inputs (EN and ). These inputs control all four drivers

and turn off the current outputs in the disabled state to reduce

the quiescent power consumption to typically 10 mW.

The device accepts low voltage TTL/CMOS logic signals and

converts them to a differential current output of typically ±±.5 mA

for driving a transmission medium such as a twisted pair cable.

The transmitted signal develops a differential voltage of typi-

cally ±±50 mV across a termination resistor at the receiving end.

This voltage is converted back to a TTL/CMOS logic level by an

LVDS receiver.

The ADN4665 offers a new solution to high speed, point-to-point

data transmission and offers a low power alternative to emitter-

coupled logic (ECL) or positive emitter-coupled logic (PECL).

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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与ADN4665ARZ相关器件

型号	品牌	描述	获取价格	数据表
ADN4665ARZ-REEL7	ADI	3 V, LVDS, Quad, CMOS Differential Line Driver	获取价格
ADN4666	ADI	3 V, LVDS, Quad CMOS Differential Line Receiver	获取价格
ADN4666ARUZ	ADI	3 V, LVDS, Quad CMOS Differential Line Receiver	获取价格
ADN4666ARUZ-REEL7	ADI	3 V, LVDS, Quad CMOS Differential Line Receiver	获取价格
ADN4666ARZ	ADI	3 V, LVDS, Quad CMOS Differential Line Receiver	获取价格
ADN4666ARZ-REEL7	ADI	3 V, LVDS, Quad CMOS Differential Line Receiver	获取价格

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