ADL5303

更新时间： 2024-02-21 14:00:41

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
24页	468K
描述
160 dB Range 100 pA to 10 mA Low Cost Logarithmic Converter

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ADL5303 技术参数

Source Url Status Check Date：	2013-05-01 14:56:39.134	是否无铅：	含铅
是否Rohs认证：	符合	生命周期：	Active
包装说明：	HVQCCN, LCC16,.12SQ,20	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	风险等级：	5.57
Is Samacsys：	N	模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	S-XQCC-N16	JESD-609代码：	e3
长度：	3 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC16,.12SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	0.8 mm	子类别：	Other Analog ICs
最大供电电流 (Isup)：	5.6 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	3 mm
Base Number Matches：	1

ADL5303 数据手册

160 dB Range 100 pA to 10 mA

Low Cost Logarithmic Converter

Data Sheet

ADL5303

FEATURES

SIMPLIFIED BLOCK DIAGRAM

VPS2

PWDN

VPS1

Optimized for fiber optic photodiode interfacing

8 full decades of range

ADL5303

VREF

Law conformance: 0.1 dB from 1 nA to 1 mA

Single-supply operation: 3.0 V to 5.5 V

Complete and temperature stable

PDB

BIAS

VREF

VPDB

~10kΩ

0.5V

VSUM

INPT

VLOG

BFIN

Accurate laser trimmed scaling

TEMPERATURE

COMPENSATION

Logarithmic slope of 10 mV/dB (at the VLOG pin)

Basic logarithmic intercept at 100 pA

Easy adjustment of slope and intercept

Output bandwidth of 10 MHz, 15 V/μs slew rate

Miniature 16-lead package (LFCSP)

5kΩ

VSUM

BFNG

Low power: ~4.5 mA quiescent current (enabled)

GND

ACOM

GND

VOUT

APPLICATIONS

Figure 1.

High accuracy optical power measurement

Wide range baseband log compression

Versatile detector for APC loops

GENERAL DESCRIPTION

The ADL5303 is a monolithic logarithmic detector optimized

for the measurement of low frequency signal power in fiber

optic systems and offers a large dynamic range in a versatile and

easily used form. Wide measurement range and accuracy are

achieved using proprietary design and precise laser trimming.

The ADL5303 requires only a single positive supply, V_PS, of 5 V.

When using low supply voltages, the log slope can be altered to

fit the available span. Low quiescent current and chip disable

facilitate use in battery-operated applications.

input pin INPT is flanked by the VSUM guard pins that track

the voltage at the summing node. Connecting the exposed pad

of the device to the VSUM pins provides a continuous guard to

minimize leakage into the INPT pin.

The default value of the logarithmic slope at the VLOG output

is set by an internal 5 kΩ resistor. Logarithmic slope can be

lowered with an external shunt resistor or increased using the

buffer and a pair of external feedback resistors. The addition of

a capacitor at the VLOG pin provides a simple low-pass filter.

The intermediate voltage, V_LOG, is buffered in an output stage

that can swing to within about 100 mV of ground and the posi-

tive supply, V_PS, and provides a peak current drive capacity of

20 mA. An on-board 2 V reference is provided to facilitate

the repositioning of the intercept. The incremental bandwidth

of a translinear logarithmic amplifier inherently diminishes

for small input currents. At I_PD=1 nA, the bandwidth of the

ADL5303 is approximately 2 kHz increasing in proportion to

The input current, I_PD, flows in the collector of an optimally

scaled NPN transistor, connected in a feedback path around a

low offset JFET amplifier. The current summing input node

operates at a constant voltage, independent of current, with

a default value of 0.5 V; this may be adjusted over a wide range.

An adaptive biasing scheme is provided for reducing photo-

diode dark current at very low light input levels. The VPDB pin

applies approximately 0.1 V reverse bias across the photodiode

for I_PD= 100 pA, rising linearly to 2.0 V of reverse bias at I_PD

10 mA to improve response time at higher power levels. The

I_PDup to a maximum value of 10 MHz.

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

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