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ADG621_15 PDF预览

ADG621_15

更新时间: 2024-11-27 01:12:39
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
12页 378K
描述
Dual SPST Switches

ADG621_15 数据手册

 浏览型号ADG621_15的Datasheet PDF文件第2页浏览型号ADG621_15的Datasheet PDF文件第3页浏览型号ADG621_15的Datasheet PDF文件第4页浏览型号ADG621_15的Datasheet PDF文件第5页浏览型号ADG621_15的Datasheet PDF文件第6页浏览型号ADG621_15的Datasheet PDF文件第7页 
CMOS 5 V/+5 V,  
4 Ω Dual SPST Switches  
ADG621/ADG622/ADG623  
FE ATURES  
FUNCTIONAL BLOCK DIAGRAMS  
5.5 Ω (maximum) on resistance  
0.9 Ω (maximum) on resistance flatness  
2.7 V to 5.5 V single supply  
ADG621  
S1  
IN1  
D1  
2.7 V to 5.5 V dual supply  
D2  
Rail-to-rail operation  
IN2  
S2  
10-lead MSOP package  
Typical power consumption (<0.01 µW)  
TTL-/CMOS-compatible inputs  
NOTES  
1. SWITCHES SHOWN FORA LOGIC 0 INPUT  
Figure 1.  
APPLICATIONS  
Automatic test equipment  
Power routing  
ADG622  
Communication systems  
Data acquisition systems  
Sample-and-hold systems  
Avionics  
Relay replacements  
Battery-powered systems  
S1  
IN1  
D1  
D2  
IN2  
S2  
NOTES  
1. SWITCHES SHOWN FORA LOGIC 0 INPUT  
GENERAL DESCRIPTION  
Figure 2.  
The ADG621/ADG622/ADG623 are monolithic, CMOS,  
single-pole, single-throw (SPST) switches. Each switch of the  
ADG621/ADG622/ADG623 conducts equally well in both  
directions when on.  
ADG623  
S1  
IN1  
D1  
The ADG621/ADG622/ADG623 contain two independent  
switches. The ADG621 and ADG622 differ only in that both  
switches are normally open and normally closed. In the ADG623,  
Switch 1 is normally open, and Switch 2 is normally closed. The  
ADG623 exhibits break-before-make switching action.  
D2  
IN2  
S2  
NOTES  
1. SWITCHES SHOWN FORA LOGIC 0 INPUT  
The ADG621/ADG622/ADG623 offer low on resistance of  
4 Ω, which is matched to within 0.25 Ω between channels.  
These switches also provide low power dissipation yet give  
high switching speeds. The ADG621/ADG622/ADG623 are  
available in a 10-lead MSOP package.  
Figure 3.  
PRODUCT HIGHLIGHTS  
1. Low on resistance, RON (4 Ω typical).  
2. Dual 2.7 V to 5.5 V or single +2.7 V to +5.5 V.  
3. Low power dissipation; CMOS construction ensures low  
power dissipation.  
4. Tiny 10-lead MSOP package.  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibilityisassumedbyAnalog Devices for its use, norforany infringements ofpatents or other  
rightsofthirdpartiesthat mayresult fromitsuse.Specificationssubjectto changewithoutnotice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarksandregisteredtrademarksarethepropertyoftheirrespective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
www.analog.com  
Fax: 781.461.3113 ©2001–2009 Analog Devices, Inc. All rights reserved.  
 
 
 
 
 

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