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ADF4156

更新时间: 2024-11-30 03:17:47
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 421K
描述
6 GHz Fractional-N Frequency Synthesizer

ADF4156 数据手册

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6 GHz Fractional-N Frequency Synthesizer  
ADF4156  
FEATURES  
GENERAL DESCRIPTION  
RF bandwidth to 6 GHz  
The ADF4156 is a 6 GHz fractional-N frequency synthesizer  
that implements local oscillators in the upconversion and  
downconversion sections of wireless receivers and transmitters.  
It consists of a low noise digital phase frequency detector  
(PFD), a precision charge pump, and a programmable reference  
divider. There is a sigma-delta (Σ-Δ) based fractional interpolator  
to allow programmable fractional-N division. The INT, FRAC,  
and MOD registers define an overall N divider (N = (INT +  
(FRAC/MOD))). The RF output phase is programmable for  
applications that require a particular phase relationship between  
the output and the reference. The ADF4156 also features cycle  
slip reduction circuitry leading to faster lock times without the  
need for modifications to the loop filter.  
2.7 V to 3.3 V power supply  
Separate VP allows extended tuning voltage  
Programmable fractional modulus  
Programmable charge pump currents  
3-wire serial interface  
Digital lock detect  
Power-down mode  
Pin compatible with  
ADF4110/ADF4111/ADF4112/ADF4113/ADF4106/  
ADF4153 and ADF4154 frequency synthesizers  
Programmable RF output phase  
Loop filter design possible with ADISimPLL  
Cycle slip reduction for faster lock times  
Control of all on-chip registers is via a simple 3-wire interface.  
The device operates with a power supply ranging from 2.7 V to  
3.3 V and can be powered down when not in use.  
APPLICATIONS  
CATV equipment  
Base stations for mobile radio (WiMAX, GSM, PCS, DCS,  
SuperCell 3G, CDMA, WCDMA)  
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)  
Wireless LANs, PMR  
Communications test equipment  
FUNCTIONAL BLOCK DIAGRAM  
AV  
DD  
DV  
DD  
V
R
SET  
P
ADF4156  
REFERENCE  
5-BIT  
R COUNTER  
×2  
REF  
IN  
DOUBLER  
/2  
DIVIDER  
+
PHASE  
CP  
CHARGE  
PUMP  
FREQUENCY  
DETECTOR  
V
DD  
HIGH Z  
CSR  
DGND  
LOCK  
DETECT  
CURRENT  
SETTING  
OUTPUT  
MUX  
MUXOUT  
SD  
OUT  
V
DD  
RFCP4 RFCP3 RFCP2 RFCP1  
R
DIV  
DIV  
RF  
RF  
A
B
IN  
N COUNTER  
N
IN  
THIRD ORDER  
FRACTIONAL  
INTERPOLATOR  
CE  
CLOCK  
DATA  
LE  
FRACTION MODULUS  
INTEGER  
REG  
32-BIT  
DATA  
REGISTER  
REG  
REG  
AGND  
DGND  
CPGND  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2006 Analog Devices, Inc. All rights reserved.  
 

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