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ADC3224IRGZT PDF预览

ADC3224IRGZT

更新时间: 2024-02-19 11:53:20
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
77页 3564K
描述
Dual Channel

ADC3224IRGZT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:48
Reach Compliance Code:compliantECCN代码:3A991C2
Factory Lead Time:6 weeks风险等级:1.72
最大模拟输入电压:2 V最小模拟输入电压:-2 V
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:S-PQCC-N48
JESD-609代码:e4长度:7 mm
湿度敏感等级:3模拟输入通道数量:2
位数:12功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式:SERIAL封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
采样速率:125 MHz座面最大高度:1 mm
标称供电电压:1.8 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

ADC3224IRGZT 数据手册

 浏览型号ADC3224IRGZT的Datasheet PDF文件第2页浏览型号ADC3224IRGZT的Datasheet PDF文件第3页浏览型号ADC3224IRGZT的Datasheet PDF文件第4页浏览型号ADC3224IRGZT的Datasheet PDF文件第5页浏览型号ADC3224IRGZT的Datasheet PDF文件第6页浏览型号ADC3224IRGZT的Datasheet PDF文件第7页 
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ADC3221, ADC3222, ADC3223, ADC3224  
SBAS672B JULY 2014REVISED MARCH 2016  
ADC322x  
Dual-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters  
1 Features  
3 Description  
The ADC322x are a high-linearity, ultra-low power,  
dual-channel, 12-bit, 25-MSPS to 125-MSPS, analog-  
to-digital converter (ADC) family. The devices are  
designed specifically to support demanding, high  
input frequency signals with large dynamic range  
requirements. An input clock divider allows more  
flexibility for system clock architecture design and the  
1
Dual Channel  
12-Bit Resolution  
Single Supply: 1.8 V  
Serial LVDS Interface (SLVDS)  
Flexible Input Clock Buffer with Divide-by-1, -2, -4  
SNR = 70.2 dBFS, SFDR = 87 dBc at  
fIN = 70 MHz  
SYSREF  
input  
enables  
complete  
system  
synchronization. The ADC322x family supports serial  
low-voltage differential signaling (LVDS) in order to  
reduce the number of interface lines, thus allowing for  
high system integration density. The serial LVDS  
interface is two-wire, where each ADC data are  
serialized and output over two LVDS pairs. An  
internal phase-locked loop (PLL) multiplies the  
incoming ADC sampling clock to derive the bit clock  
that is used to serialize the 12-bit output data from  
each channel. In addition to the serial data streams,  
the frame and bit clocks are also transmitted as  
LVDS outputs.  
Ultra-Low Power Consumption:  
116 mW/Ch at 125 MSPS  
Channel Isolation: 105 dB  
Internal Dither and Chopper  
Support for Multi-Chip Synchronization  
Pin-to-Pin Compatible with 14-Bit Version  
Package: VQFN-48 (7 mm × 7 mm)  
2 Applications  
Multi-Carrier, Multi-Mode Cellular Base Stations  
Radar and Smart Antenna Arrays  
Munitions Guidance  
Device Information(1)  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
ADC322x  
VQFN (48)  
7.00 mm × 7.00 mm  
Motor Control Feedback  
(1) For all available packages, see the orderable addendum at  
the end of the datasheet.  
Network and Vector Analyzers  
Communications Test Equipment  
Nondestructive Testing  
space  
space  
space  
space  
space  
space  
Microwave Receivers  
Software-Defined Radios (SDRs)  
Quadrature and Diversity Radio Receivers  
Handheld Radio and Instrumentation  
Performance at fS = 125 MSPS, fIN = 10 MHz  
(SNR = 70.6 dBFS, SFDR = 100 dBc)  
0
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-90  
-100  
-110  
-120  
0
12.5  
25  
37.5  
50  
62.5  
Frequency (MHz)  
D201  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 

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