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ADC16DV160CILQ/NOPB PDF预览

ADC16DV160CILQ/NOPB

更新时间: 2024-01-04 18:44:47
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
32页 1468K
描述
IC 2-CH 16-BIT FLASH METHOD ADC, SERIAL/PARALLEL ACCESS, QCC68, 10 X 10 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LLP-68, Analog to Digital Converter

ADC16DV160CILQ/NOPB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:68
Reach Compliance Code:unknown风险等级:5.83
最大模拟输入电压:2.4 V最小模拟输入电压:
最长转换时间:0.0063 µs转换器类型:ADC, FLASH METHOD
JESD-30 代码:S-XQCC-N68JESD-609代码:e3
长度:10 mm湿度敏感等级:4
模拟输入通道数量:2位数:16
功能数量:1端子数量:68
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式:SERIAL, PARALLEL, WORD
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260采样速率:160 MHz
采样并保持/跟踪并保持:SAMPLE座面最大高度:1 mm
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:10 mm

ADC16DV160CILQ/NOPB 数据手册

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PRELIMINARY  
January 14, 2010  
ADC16DV160  
Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital  
Converter with DDR LVDS Outputs  
On-chip low jitter duty-cycle stabilizer  
General Description  
Power-down and sleep modes  
The ADC16DV160 is a monolithic dual channel high perfor-  
Output fixed pattern generation  
mance CMOS analog-to-digital converter capable of convert-  
ing analog input signals into 16-bit digital words at rates up to  
160 Mega Samples Per Second (MSPS). This converter uses  
a differential, pipelined architecture with digital error correc-  
tion and an on-chip sample-and-hold circuit to minimize pow-  
er consumption and external component count while provid-  
ing excellent dynamic performance. Automatic power-up  
calibration enables excellent dynamic performance and re-  
duces part-to-part variation, and the ADC16DV160 can be re-  
calibrated at any time through the 3-wire Serial Peripheral  
Interface (SPI). An integrated low noise and stable voltage  
reference and differential reference buffer amplifier eases  
board level design. The on-chip duty cycle stabilizer with low  
additive jitter allows a wide range of input clock duty cycles  
without compromising dynamic performance. A unique sam-  
ple-and-hold stage yields a full-power bandwidth of 1.4 GHz.  
The interface between the ADC16DV160 and a receiver block  
can be easily verified and optimized via fixed pattern gener-  
ation and output clock position features. The digital data is  
provided via dual data rate LVDS outputs – making possible  
the 68-pin, 10 mm x 10 mm LLP package. The ADC16DV160  
operates on dual power supplies of +1.8V and +3.0V with a  
power-down feature to reduce power consumption to very low  
levels while allowing fast recovery to full operation.  
Output clock position adjustment  
3-wire SPI  
Offset binary or 2's complement data format  
68-pin LLP package (10x10x0.8, 0.5mm pin-pitch)  
Key Specifications  
Resolution  
16 Bits  
160 MSPS  
ꢀꢀ  
Conversion Rate  
SNR  
(@FIN = 30 MHz)  
(@FIN = 197 MHz)  
SFDR  
78 dBFS (typ)  
76 dBFS (typ)  
ꢀꢀ  
95 dBFS (typ)  
(@FIN = 30 MHz)  
(@FIN = 197 MHz)  
Full Power Bandwidth  
Power Consumption  
89 dBFS (typ)  
1.4 GHz (typ)  
ꢀꢀ  
-Core per channel  
-LVDS Driver  
612 mW (typ)  
117 mW (typ)  
-Total  
1.3W (typ)  
-40°C ~ 85°C  
Operating Temperature Range  
Applications  
Features  
Multi-carrier, Multi-standard Base Station Receivers  
-MC-GSM/EDGE, CDMA2000, UMTS, LTE and WiMAX  
Low power consumption  
On-chip precision reference and sample-and-hold circuit  
On-chip automatic calibration during power-up  
Dual data rate LVDS output port  
High IF Sampling Receivers  
Diversity Channel Receivers  
Test and Measurement Equipment  
Communications Instrumentation  
Portable Instrumentation  
Dual Supplies: 1.8V and 3.0V operation  
Selectable input range: 2.4, 2.0, 1.5 and 1.0VPP  
Sampling edge flipping with clock divider by 2 option  
Internal clock divide by 1 or 2  
© 2010 National Semiconductor Corporation  
301014  
www.national.com  

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