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ADC12L066 PDF预览

ADC12L066

更新时间: 2024-11-27 11:12:07
品牌 Logo 应用领域
德州仪器 - TI 转换器模数转换器
页数 文件大小 规格书
38页 1369K
描述
12 位、66MSPS、450MHz 输入带宽模数转换器 (ADC)

ADC12L066 数据手册

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ADC12L066  
www.ti.com  
SNAS153I NOVEMBER 2001REVISED MARCH 2013  
ADC12L066 12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-  
Hold  
Check for Samples: ADC12L066  
1
FEATURES  
DESCRIPTION  
The ADC12L066 is a monolithic CMOS analog-to-  
digital converter capable of converting analog input  
signals into 12-bit digital words at 66 Megasamples  
per second (Msps), minimum, with typical operation  
possible up to 80 Msps. This converter uses a  
differential, pipeline architecture with digital error  
correction and an on-chip sample-and-hold circuit to  
minimize die size and power consumption while  
providing excellent dynamic performance. A unique  
sample-and-hold stage yields a full-power bandwidth  
of 450 MHz. Operating on a single 3.3V power  
supply, this device consumes just 357 mW at 66  
Msps, including the reference current. The Power  
Down feature reduces power consumption to just 50  
mW.  
23  
Single Supply Operation  
Low Power Consumption  
Power Down Mode  
On-Chip Reference Buffer  
APPLICATIONS  
Ultrasound and Imaging  
Instrumentation  
Cellular Base Stations/Communications  
Receivers  
Sonar/Radar  
xDSL  
Wireless Local Loops  
Data Acquisition Systems  
DSP Front Ends  
The differential inputs provide a full scale input swing  
equal to ±VREF with the possibility of a single-ended  
input. Full use of the differential input is  
recommended for optimum performance. For ease of  
use, the buffered, high impedance, single-ended  
reference input is converted on-chip to a differential  
reference for use by the processing circuitry. Output  
data format is 12-bit offset binary.  
KEY SPECIFICATIONS  
Resolution: 12 Bits  
Conversion Rate: 66 Msps  
This device is available in the 32-lead LQFP package  
and will operate over the industrial temperature range  
of 40°C to +85°C. An evaluation board is available  
to facilitate the evaluation process.  
Full Power Bandwidth: 450 MHz  
DNL: ±0.4 LSB (typ)  
SNR (fIN = 10 MHz): 66 dB (typ)  
SFDR (fIN = 10 MHz): 80 dB (typ)  
Data Latency: 6 Clock Cycles  
Supply Voltage: +3.3V ± 300 mV  
Power Consumption, 66 MHz: 357 mW (typ)  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
TRI-STATE is a registered trademark of National Semiconductor Corporation.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2001–2013, Texas Instruments Incorporated  

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