Datasheet > ADC12DJ5200RF_V01

ADC12DJ5200RF_V01

更新时间： 2024-11-26 02:50:55

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德州仪器 - TI		/
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描述
ADC12DJ5200RF 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC)

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ADC12DJ5200RF

www.ti.com

SLVSEN9B – APRIL 2019 – REVISED DECEMBER 2020

ADC12DJ5200RF 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel,

12-bit, RF-Sampling Analog-to-Digital Converter (ADC)

1 Features

3 Description

•

ADC core:

– 12-bit resolution

– Up to 10.4 GSPS in single-channel mode

– Up to 5.2 GSPS in dual-channel mode

Performance specifications:

The ADC12DJ5200RF device is an RF-sampling,

giga-sample, analog-to-digital converter (ADC) that

can directly sample input frequencies from DC to

above 10 GHz. ADC12DJ5200RF can be configured

as a dual-channel, 5.2 GSPS ADC or single-channel,

10.4 GSPS ADC. Support of a useable input

frequency range of up to 10 GHz enables direct RF

sampling of L-band, S-band, C-band, and X-band for

frequency agile systems.

•

– Noise floor (–20 dBFS, V_FS= 1 V_PP-DIFF):

•

Dual-channel mode: –151.8 dBFS/Hz

Single-channel mode: –154.4 dBFS/Hz

– ENOB (dual channel, F_IN= 2.4 GHz): 8.6 Bits

Buffered analog inputs with V_CMIof 0 V:

– Analog input bandwidth (–3 dB): 8 GHz

– Usable input frequency range: > 10 GHz

– Full-scale input voltage (V_FS, default): 0.8 V_PP

Noiseless aperture delay (t_AD) adjustment:

– Precise sampling control: 19-fs Step

– Simplifies synchronization and interleaving

– Temperature and voltage invariant delays

Easy-to-use synchronization features:

– Automatic SYSREF timing calibration

– Timestamp for sample marking

The ADC12DJ5200RF uses a high-speed JESD204C

output interface with up to 16 serialized lanes

supporting up to 17.16 Gbps line rate. Deterministic

latency and multi-device synchronization is supported

through JESD204C subclass-1. The JESD204C

interface can be configured to trade-off line rate and

number of lanes. Both 8b/10b and 64b/66b data

encoding schemes are supported. 64b/66b encoding

supports forward error correction (FEC) for improved

bit error rates. The interface is backwards compatible

with JESD204B receivers.

•

Innovative

synchronization

features,

including

noiseless aperture delay adjustment and SYSREF

windowing, simplify system design for multi-channel

applications. Optional digital down converters (DDCs)

are available to provide digital conversion to

baseband and to reduce the interface rate. A

programmable FIR filter allows on-chip equalization.

JESD204C serial data interface:

– Maximum lane rate: 17.16 Gbps

– Support for 64b/66b and 8b/10b encoding

– 8b/10b modes are JESD204B compatible

Optional digital down-converters (DDC):

– 4x, 8x, 16x and 32x complex decimation

– Four independent 32-Bit NCOs per DDC

Peak RF Input Power (Diff): +26.5 dBm (+ 27.5

dBFS, 560x fullscale power)

•

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

ADC12DJ5200RF

FCBGA (144) 10.00 mm × 10.00 mm

(1) For all available packages, see the package option

addendum at the end of the data sheet.

•

Programmable FIR filter for equalization

Power consumption: 4 W

Power supplies: 1.1 V, 1.9 V

NCOA0 NCOA1 NCOB0 NCOB1 CALTRG PD

SCLK

SDI

SDO

SCS\

SPI Registers and

Device Control

2 Applications

TMSTP+

TMSTP-

DA0+

DA0-

Crossbar MUX

or Interleaving

•

Oscilloscopes and wideband digitizers

Communications testers (802.11ad, 5G)

Electronic warfare (SIGINT, ELINT)

Satellite communications (SATCOM)

RF-sampling software-defined radio (SDR)

Spectrometry

Input

MUX

JESD204C

Link

ADC

INA+

INA-

Digital Down

Converter (DDC)

Block

DA7+

DA7-

Over-

range

PFIR

Block

DDC Options:

DDC Bypass

Decimate-by-4

Decimate-by-8

Decimate-by-16

Decimate-by-32

SYNCSE\

DB0+

DB0-

INB+

INB-

Input

MUX

JESD204C

Link

ADC

DB7+

DB7-

Aperture

Delay Adjust

JMODE

CLK+

CLK-

Clock Distribution

and Synchronization

ORA0

ORA1

ORB0

ORB1

Status

Indicators

SYSREF+

SYSREF-

SYSREF

Windowing

CALSTAT

TDIODE+

TDIODE-

ADC12DJ5200RF Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Product Folder Links: ADC12DJ5200RF

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与ADC12DJ5200RF_V01相关器件

型号	品牌	获取价格	描述	数据表
ADC12DJ5200RFAAV	TI	获取价格	具有双通道 5.2GSPS 或单通道 10.4GSPS 的射频采样 12 位 ADC \|
ADC12DJ5200RFAAVT	TI	获取价格	具有双通道 5.2GSPS 或单通道 10.4GSPS 的射频采样 12 位 ADC \|
ADC12DJ5200RFZEG	TI	获取价格	ADC12DJ5200RF 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel, 12-bit, RF-Sampling Analo
ADC12DJ5200RFZEGT	TI	获取价格	ADC12DJ5200RF 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel, 12-bit, RF-Sampling Analo
ADC12DJ5200SE	TI	获取价格	具有双通道 5.2GSPS 或单通道 10.4GSPS 的单端输入射频采样 12 位 AD
ADC12DJ5200-SEP	TI	获取价格	Radiation-tolerant, 30-krad, 12-bit, dual 5.2-GSPS or single 10.4-GSPS ADC
ADC12DJ5200-SP	TI	获取价格	耐辐射加固保障 (RHA)、300krad、12 位、双通道 5.2GSPS 或单通道 1
ADC12DJ800	TI	获取价格	ADC12xJ800 Quad, Dual, Single Channel, 800-MSPS, 12-bit, Analog-to-Digital Converter (ADC)
ADC12DJ800AAV	TI	获取价格	ADC12xJ800 Quad, Dual, Single Channel, 800-MSPS, 12-bit, Analog-to-Digital Converter (ADC)
ADC12DJ800AAVQ1	TI	获取价格	ADC12xJ800-Q1 Quad, Dual, Single Channel, 800-MSPS, 12-bit, Analog-to-Digital Converter (A

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