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ADC1212D125HN/C1 PDF预览

ADC1212D125HN/C1

更新时间： 2024-11-24 03:31:39
品牌 Logo 应用领域
艾迪悌 - IDT 转换器
页数 文件大小 规格书
38页 1059K
描述
PROPRIETARY METHOD ADC, PQCC64, 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64

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ADC1212D125HN/C1 技术参数

生命周期：Obsolete零件包装代码：QFN
包装说明：,针数：64
Reach Compliance Code：unknown风险等级：5.73
转换器类型：ADC, PROPRIETARY METHODJESD-30 代码：S-PQCC-N64
端子数量：64输出位码：OFFSET BINARY
封装主体材料：PLASTIC/EPOXY封装形状：SQUARE
封装形式：CHIP CARRIER认证状态：Not Qualified
表面贴装：YES端子形式：NO LEAD
端子位置：QUAD

ADC1212D125HN/C1 数据手册

 浏览型号ADC1212D125HN/C1的Datasheet PDF文件第2页浏览型号ADC1212D125HN/C1的Datasheet PDF文件第3页浏览型号ADC1212D125HN/C1的Datasheet PDF文件第4页浏览型号ADC1212D125HN/C1的Datasheet PDF文件第5页浏览型号ADC1212D125HN/C1的Datasheet PDF文件第6页浏览型号ADC1212D125HN/C1的Datasheet PDF文件第7页 
ADC1212D series  
Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;  
CMOS or LVDS DDR digital outputs  
Rev. 01 — 6 August 2010  
Preliminary data sheet  
1. General description  
The ADC1212D is a dual channel 12-bit Analog-to-Digital Converter (ADC) optimized for  
high dynamic performances and low power consumption at sample rates up to 125 Msps.  
Pipelined architecture and output error correction ensure the ADC1212D is accurate  
enough to guarantee zero missing codes over the entire operating range. Supplied from a  
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in  
Complementary Metal Oxide Semiconductor (CMOS) mode, because of a separate digital  
output supply. It supports the Low Voltage Differential Signalling (LVDS) Double Data Rate  
(DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to  
easily configure the ADC. The device also includes an SPI programmable full-scale to  
allow a flexible input voltage range of 1 V to 2 V (peak-to-peak). With excellent dynamic  
performance from the baseband to input frequencies of 170 MHz or more, the ADC1212D  
is ideal for use in communications, imaging and medical applications.  
2. Features and benefits  
„ SNR, 70.5 dBFS  
„ Input bandwidth, 600 MHz  
„ SFDR, 86 dBc  
„ Power dissipation, 855 mW at 80 Msps  
„ Serial Peripheral Interface (SPI)  
„ Duty cycle stabilizer  
„ Sample rate up to 125 Msps  
„ Clock input divider by 2 for less jitter  
contribution  
„ Single 3 V supply  
„ Fast OuT-of-Range (OTR) detection  
„ INL: ± 0.25 LSB; DNL: ± 0.12 LSB  
„ Flexible input voltage range:  
1 V to 2 V (p-p)  
„ CMOS or LVDS DDR digital outputs  
„ Offset binary, two’s complement, gray  
code  
„ Pin and software compatible with  
„ Power-down and Sleep modes  
ADC1412D series.  
„ HVQFN64 package  
3. Applications  
„ Wireless and wired broadband  
„ Spectral analysis  
communications  
„ Portable instrumentation  
„ Imaging systems  
„ Ultrasound equipment  
„ Software defined radio  
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ADC12130CIN/NOPB TI

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