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ADC1210S125HN/C1,5 PDF预览

ADC1210S125HN/C1,5

更新时间: 2024-11-19 14:40:47
品牌 Logo 应用领域
艾迪悌 - IDT 转换器
页数 文件大小 规格书
37页 363K
描述
IC IC,A/D CONVERTER,SINGLE,12-BIT,CMOS,LLCC,40PIN, Analog to Digital Converter

ADC1210S125HN/C1,5 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:QCCN, LCC40,.24SQ,20
Reach Compliance Code:compliantECCN代码:3A991.C.2
HTS代码:8542.39.00.01风险等级:5.83
最大模拟输入电压:2 V转换器类型:A/D CONVERTER
JESD-30 代码:S-PQCC-N40JESD-609代码:e3
最大线性误差 (EL):0.03%湿度敏感等级:1
位数:12功能数量:1
端子数量:40最高工作温度:85 °C
最低工作温度:-40 °C输出位码:OFFSET BINARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCN
封装等效代码:LCC40,.24SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:3 V认证状态:Not Qualified
子类别:Analog to Digital Converters标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

ADC1210S125HN/C1,5 数据手册

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ADC1210S series  
Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;  
CMOS or LVDS DDR digital outputs  
Rev. 03 — 2 July 2012  
Product data sheet  
1. General description  
The ADC1210S is a single-channel 12-bit Analog-to-Digital Converter (ADC) optimized for  
high dynamic performance and low power consumption at sample rates up to 125 Msps.  
Pipelined architecture and output error correction ensure the ADC1210S is accurate  
enough to guarantee zero missing codes over the entire operating range. Supplied from a  
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode  
because of a separate digital output supply. It supports the Low Voltage Differential  
Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated  
Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device  
also includes a programmable full-scale SPI to allow a flexible input voltage range from  
1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to  
input frequencies of 170 MHz or more, the ADC1210S is ideal for use in communications,  
imaging and medical applications.  
2. Features and benefits  
SNR, 70 dBFS; SFDR, 86 dBc  
Input bandwidth, 600 MHz  
Sample rate up to 125 Msps  
12-bit pipelined ADC core  
Clock input divided by 2 for less jitter  
Single 3 V supply  
Power dissipation, 430 mW at 80 Msps  
Serial Peripheral Interface (SPI)  
Duty cycle stabilizer  
Fast OuT-of-Range (OTR) detection  
Flexible input voltage range: 1 V (p-p) to Offset binary, two’s complement, gray  
2 V (p-p)  
code  
CMOS or LVDS DDR digital outputs  
Pin compatible with the ADC1410S  
series and the ADC1010S series  
Power-down and Sleep modes  
HVQFN40 package  
3. Applications  
Wireless and wired broadband  
Portable instrumentation  
communications  
Spectral analysis  
Imaging systems  
Ultrasound equipment  
Software defined radio  
®

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