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ADC11DL066CIVS PDF预览

ADC11DL066CIVS

更新时间: 2024-11-26 21:53:51
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
23页 617K
描述
Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D Converter w/Internal Reference

ADC11DL066CIVS 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:TQFP-64Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.43最大模拟输入电压:1.8 V
最小模拟输入电压:0.5 V转换器类型:ADC, PROPRIETARY METHOD
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm最大线性误差 (EL):0.0781%
湿度敏感等级:3模拟输入通道数量:1
位数:11功能数量:2
端子数量:64最高工作温度:85 °C
最低工作温度:-40 °C输出位码:BINARY, 2'S COMPLEMENT BINARY
输出格式:PARALLEL, WORD封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装等效代码:TQFP64,.47SQ
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified采样速率:66 MHz
采样并保持/跟踪并保持:SAMPLE座面最大高度:1.2 mm
子类别:Analog to Digital Converters标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:10 mmBase Number Matches:1

ADC11DL066CIVS 数据手册

 浏览型号ADC11DL066CIVS的Datasheet PDF文件第2页浏览型号ADC11DL066CIVS的Datasheet PDF文件第3页浏览型号ADC11DL066CIVS的Datasheet PDF文件第4页浏览型号ADC11DL066CIVS的Datasheet PDF文件第5页浏览型号ADC11DL066CIVS的Datasheet PDF文件第6页浏览型号ADC11DL066CIVS的Datasheet PDF文件第7页 
March 2004  
ADC11DL066  
Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D  
Converter w/Internal Reference  
General Description  
Features  
n Single +3.3V supply operation  
n Internal sample-and-hold  
n Outputs 2.4V to 3.3V compatible  
n Power down mode  
The ADC11DL066 is a dual, low power monolithic CMOS  
analog-to-digital converter capable of converting analog in-  
put signals into 11-bit digital words at 66 Megasamples per  
second (MSPS), minimum. This converter uses a differential,  
pipeline architecture with digital error correction and an on-  
chip sample-and-hold circuit to minimize die size and power  
consumption while providing excellent dynamic performance  
and a 450 MHz Full Power Bandwidth. Operating on a single  
3.3V power supply, the ADC11DL066 achieves 10.3 effective  
bits and consumes just 686 mW at 66 MSPS, including the  
reference current. The Power Down feature reduces power  
consumption to 75 mW.  
n On-chip reference  
Key Specifications  
n Resolution  
11 Bits  
0.25 LSB (typ)  
64 dB (typ)  
80 dB (typ)  
6 Clock Cycles  
n DNL  
n SNR (fIN = 10 MHz)  
n SFDR (fIN = 10 MHz)  
n Data Latency  
n Power Consumption  
— Operating  
The differential inputs provide a full scale differential input  
swing equal to 2 times VREF with the possibility of a single-  
ended input. Full use of the differential input is recom-  
mended for optimum performance. The digital outputs from  
the two ADCs are available on separate 11-bit buses with an  
output data format choice of offset binary or two’s comple-  
ment.  
686 mW (typ)  
75 mW (typ)  
— Power Down  
Applications  
n Ultrasound and Imaging  
n Instrumentation  
n Communications Receivers  
n Sonar/Radar  
To ease interfacing to lower voltage systems, the digital  
output driver power pins of the ADC11DL066 can be con-  
nected to a separate supply voltage in the range of 2.4V to  
the digital supply voltage.  
n xDSL  
n Cable Modems  
n DSP Front Ends  
This device is available in the 64-lead TQFP package and  
will operate over the industrial temperature range of −40˚C to  
+85˚C. An evaluation board is available to ease the evalua-  
tion process.  
Connection Diagram  
20077301  
20040326  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2004 National Semiconductor Corporation  
DS200773  
www.national.com  

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