ADC11C170LFEB

更新时间： 2024-11-24 03:54:11

品牌	Logo	应用领域
美国国家半导体 - NSC		转换器
页数	文件大小	规格书
22页	419K
描述
11-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with CMOS outputs

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ADC11C170LFEB 数据手册

July 2007

ADC11C170

11-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with

CMOS outputs

General Description

Features

The ADC11C170 is a high-performance CMOS analog-to-

digital converter capable of converting analog input signals

into 11-Bit digital words at rates up to 170 Mega Samples Per

Second (MSPS). This converter uses a differential, pipelined

architecture with digital error correction and an on-chip sam-

ple-and-hold circuit to minimize power consumption and the

external component count, while providing excellent dynamic

performance. A unique sample-and-hold stage yields a full-

power bandwidth of 1.1 GHz. The ADC11C170 operates from

dual +3.3V and +1.8V power supplies and consumes 747 mW

of power at 170 MSPS.

1.1 GHz Full Power Bandwidth

■

Internal sample-and-hold circuit

Low power consumption

Internal precision 1.0V reference

Single-ended or Differential clock modes

Clock Duty Cycle Stabilizer

Dual +3.3V and +1.8V supply operation (+/- 10%)

Power-down and Sleep modes

Offset binary or 2's complement output data format

■

Pin-compatible: ADC14155, ADC12C170, ADC11C125

The separate +1.8V supply for the digital output interface al-

lows lower power operation with reduced noise. A power-

down feature reduces the power consumption to 5 mW while

still allowing fast wake-up time to full operation. In addition

there is a sleep feature which consumes 50 mW of power and

has a faster wake-up time.

48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)

Key Specifications

Resolution

Conversion Rate

11 Bits

■

170 MSPS

65.1 dBFS (typ)

85.4 dBFS (typ)

10.5 bits (typ)

1.1 GHz (typ)

715 mW (typ)

The differential inputs provide a full scale differential input

swing equal to 2 times the reference voltage. A stable 1.0V

internal voltage reference is provided, or the ADC11C170 can

be operated with an external reference.

SNR (f_IN= 70 MHz)

SFDR (f_IN= 70 MHz)

ENOB (f_IN= 70 MHz)

Full Power Bandwidth

Power Consumption

Clock mode (differential versus single-ended) and output data

format (offset binary versus 2's complement) are pin-se-

lectable. A duty cycle stabilizer maintains performance over

a wide range of input clock duty cycles.

Applications

The ADC11C170 is pin compatible with the ADC11C125, AD-

C12C170, and ADC14155.

High IF Sampling Receivers

■

Wireless Base Station Receivers

It is available in a 48-lead LLP package and operates over the

industrial temperature range of −40°C to +85°C.

Power Amplifier Linearization

Multi-carrier, Multi-mode Receivers

Test and Measurement Equipment

Communications Instrumentation

Radar Systems

Block Diagram

30019002

300190

www.national.com

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