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ADC11C125CISQ PDF预览

ADC11C125CISQ

更新时间： 2024-11-24 06:36:19
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
24页 465K
描述
11-Bit, 125 MSPS, 1.1 GHz Bandwidth A/D Converter with CMOS Outputs

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中文翻译

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ADC11C125CISQ 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：7 X 7 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-48Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.46最大模拟输入电压：2.6 V
最小模拟输入电压：最长转换时间：0.056 µs
转换器类型：ADC, PROPRIETARY METHODJESD-30 代码：S-XQCC-N48
JESD-609代码：e0长度：7 mm
最大线性误差 (EL)：0.0405%湿度敏感等级：3
模拟输入通道数量：1位数：11
功能数量：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出位码：OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式：PARALLEL, WORD
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC48,.27SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
采样速率：125 MHz采样并保持/跟踪并保持：SAMPLE
座面最大高度：0.8 mm子类别：Analog to Digital Converters
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：7 mm
Base Number Matches：1

ADC11C125CISQ 数据手册

 浏览型号ADC11C125CISQ的Datasheet PDF文件第2页浏览型号ADC11C125CISQ的Datasheet PDF文件第3页浏览型号ADC11C125CISQ的Datasheet PDF文件第4页浏览型号ADC11C125CISQ的Datasheet PDF文件第5页浏览型号ADC11C125CISQ的Datasheet PDF文件第6页浏览型号ADC11C125CISQ的Datasheet PDF文件第7页 
April 28, 2009  
ADC11C125  
11-Bit, 125 MSPS, 1.1 GHz Bandwidth A/D Converter with  
CMOS Outputs  
General Description  
Features  
The ADC11C125 is a high-performance CMOS analog-to-  
digital converter capable of converting analog input signals  
into 11-Bit digital words at rates up to 125 Mega Samples Per  
Second (MSPS). This converter uses a differential, pipelined  
architecture with digital error correction and an on-chip sam-  
ple-and-hold circuit to minimize power consumption and the  
external component count, while providing excellent dynamic  
performance. A unique sample-and-hold stage yields a full-  
power bandwidth of 1.1 GHz. The ADC11C125 operates from  
dual +3.3V and +1.8V power supplies and consumes 608 mW  
of power at 125 MSPS.  
1.1 GHz Full Power Bandwidth  
■
■
■
■
■
■
■
■
Internal sample-and-hold circuit  
Low power consumption  
Internal precision 1.0V reference  
Single-ended or Differential clock modes  
Clock Duty Cycle Stabilizer  
Dual +3.3V and +1.8V supply operation  
Power-down and Sleep modes  
Offset binary or 2's complement output data format  
■
■
■
Pin-compatible: ADC14155, ADC12C170, ADC11C170  
The separate +1.8V supply for the digital output interface al-  
lows lower power operation with reduced noise. A power-  
down feature reduces the power consumption to 5 mW while  
still allowing fast wake-up time to full operation. In addition  
there is a sleep feature which consumes 50 mW of power and  
has a faster wake-up time.  
48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)  
Key Specifications  
Resolution  
Conversion Rate  
11 Bits  
■
■
■
■
■
■
■
125 MSPS  
65.5 dBFS (typ)  
88.2 dBFS (typ)  
10.5 bits (typ)  
1.1 GHz (typ)  
608 mW (typ)  
The differential inputs provide a full scale differential input  
swing equal to 2 times the reference voltage. A stable 1.0V  
internal voltage reference is provided, or the ADC11C125 can  
be operated with an external reference.  
SNR (fIN = 70 MHz)  
SFDR (fIN = 70 MHz)  
ENOB (fIN = 70 MHz)  
Full Power Bandwidth  
Power Consumption  
Clock mode (differential versus single-ended) and output data  
format (offset binary versus 2's complement) are pin-se-  
lectable. A duty cycle stabilizer maintains performance over  
a wide range of input clock duty cycles.  
Applications  
The ADC11C125 is pin compatible with the ADC12C170 and  
the ADC14155.  
High IF Sampling Receivers  
■
■
■
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Wireless Base Station Receivers  
It is available in a 48-lead LLP package and operates over the  
industrial temperature range of −40°C to +85°C.  
Power Amplifier Linearization  
Multi-carrier, Multi-mode Receivers  
Test and Measurement Equipment  
Communications Instrumentation  
Radar Systems  
Block Diagram  
20214002  
© 2009 National Semiconductor Corporation  
202140  
www.national.com  
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