ADC11C125
www.ti.com
SNAS387C –MAY 2007–REVISED APRIL 2013
ADC11C125 11-Bit, 125 MSPS, 1.1 GHz Bandwidth A/D Converter with CMOS Outputs
Check for Samples: ADC11C125
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FEATURES
DESCRIPTION
The ADC11C125 is
a high-performance CMOS
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1.1 GHz Full Power Bandwidth
Internal Sample-and-Hold Circuit
Low Power Consumption
analog-to-digital converter capable of converting
analog input signals into 11-Bit digital words at rates
up to 125 Mega Samples Per Second (MSPS). This
converter uses a differential, pipelined architecture
with digital error correction and an on-chip sample-
and-hold circuit to minimize power consumption and
the external component count, while providing
excellent dynamic performance. A unique sample-
and-hold stage yields a full-power bandwidth of 1.1
GHz. The ADC11C125 operates from dual +3.3V and
+1.8V power supplies and consumes 608 mW of
power at 125 MSPS.
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Internal Precision 1.0V Reference
Single-Ended or Differential Clock Modes
Clock Duty Cycle Stabilizer
Dual +3.3V and +1.8V Supply Operation
Power-Down and Sleep Modes
Offset Binary or 2's Complement Output Data
Format
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Pin-Compatible: ADC14155, ADC12C170,
ADC11C170
The separate +1.8V supply for the digital output
interface allows lower power operation with reduced
noise. A power-down feature reduces the power
consumption to 5 mW while still allowing fast wake-up
time to full operation. In addition there is a sleep
feature which consumes 50 mW of power and has a
faster wake-up time.
48-pin WQFN Package, (7x7x0.8mm, 0.5mm
Pin-Pitch)
APPLICATIONS
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High IF Sampling Receivers
Wireless Base Station Receivers
Power Amplifier Linearization
Multi-Carrier, Multi-Mode Receivers
Test and Measurement Equipment
Communications Instrumentation
Radar Systems
The differential inputs provide a full scale differential
input swing equal to 2 times the reference voltage. A
stable 1.0V internal voltage reference is provided, or
the ADC11C125 can be operated with an external
reference.
Clock mode (differential versus single-ended) and
output data format (offset binary versus 2's
complement) are pin-selectable.
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duty cycle
stabilizer maintains performance over a wide range of
input clock duty cycles.
KEY SPECIFICATIONS
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Resolution 11 Bits
The ADC11C125 is pin compatible with the
ADC12C170 and the ADC14155.
Conversion Rate 125 MSPS
SNR (fIN = 70 MHz) 65.5 dBFS (typ)
SFDR (fIN = 70 MHz) 88.2 dBFS (typ)
ENOB (fIN = 70 MHz) 10.5 bits (typ)
Full Power Bandwidth 1.1 GHz (typ)
Power Consumption 608 mW (typ)
It is available in a 48-lead WQFN package and
operates over the industrial temperature range of
−40°C to +85°C.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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