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ADC10D1500CIUT PDF预览

ADC10D1500CIUT

更新时间： 2024-11-22 11:12:43
品牌 Logo 应用领域
德州仪器 - TI 转换器模数转换器
页数 文件大小 规格书
83页 2122K
描述
10 位、双路 1.5GSPS 或单路 3.0GSPS 模数转换器 (ADC) | NXA | 292 | -40 to 85

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ADC10D1500CIUT 技术参数

生命周期：Active零件包装代码：BGA
包装说明：HBGA, BGA292,20X20,50针数：292
Reach Compliance Code：not_compliantECCN代码：3A001.A.5.A.2
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.43最大模拟输入电压：0.8 V
最小模拟输入电压：-0.8 V转换器类型：ADC, DELTA-SIGMA
JESD-30 代码：S-PBGA-B292JESD-609代码：e0
长度：27 mm最大线性误差 (EL)：0.1367%
湿度敏感等级：3模拟输入通道数量：1
位数：10功能数量：1
端子数量：292最高工作温度：85 °C
最低工作温度：-40 °C输出位码：OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式：PARALLEL, WORD封装主体材料：PLASTIC/EPOXY
封装代码：HBGA封装等效代码：BGA292,20X20,50
封装形状：SQUARE封装形式：GRID ARRAY, HEAT SINK/SLUG
峰值回流温度（摄氏度）：220采样速率：3000 MHz
采样并保持/跟踪并保持：TRACK座面最大高度：2.58 mm
标称供电电压：1.9 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：27 mm
Base Number Matches：1

ADC10D1500CIUT 数据手册

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ADC10D1000, ADC10D1500  
www.ti.com  
SNAS462Q –OCTOBER 2008–REVISED MARCH 2013  
ADC10D1000/ADC10D1500 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS  
ADC  
Check for Samples: ADC10D1000, ADC10D1500  
1
FEATURES  
DESCRIPTION  
The ADC10D1000/1500 is the latest advance in TI's  
Ultra-High-Speed ADC family. This low-power, high-  
performance CMOS analog-to-digital converter  
digitizes signals at 10-bit resolution for dual channels  
at sampling rates of up to 1.0/1.5 GSPS (Non-DES  
Mode) or for a single channel up to 2.0/3.0 GSPS  
(DES Mode). The ADC10D1000/1500 achieves  
excellent accuracy and dynamic performance while  
dissipating less than 2.8/3.6 Watts. The product is  
packaged in a leaded or lead-free 292-ball thermally  
enhanced BGA package over the rated industrial  
temperature range of -40°C to +85°C.  
2
•
Excellent Accuracy and Dynamic Performance  
Pin Compatible with ADC12D1000/1600/1800  
•
•
Low Power Consumption, Further Reduced at  
Lower Fs  
•
Internally Terminated, Buffered, Differential  
Analog Inputs  
•
•
R/W SPI Interface for Extended Control Mode  
Dual-Edge Sampling Mode, in Which the I- and  
Q-channels Sample One Input at Twice the  
Sampling Clock Rate  
•
•
Test Patterns at Output for System Debug  
The ADC10D1000/1500 builds upon the features,  
architecture and functionality of the 8-bit GHz family  
of ADCs. An expanded feature set includes AutoSync  
for multi-chip synchronization, 15-bit programmable  
gain and 12-bit plus sign programmable offset  
adjustment for each channel. The improved internal  
track-and-hold amplifier and the extended self-  
calibration scheme enable a very flat response of all  
dynamic parameters beyond Nyquist, producing  
9.1/9.0 Effective Number of Bits (ENOB) with a 100  
MHz input signal and a 1.0/1.5 GHz sample rate  
while providing a 10-18 Code Error Rate (CER)  
Programmable 15-bit Gain and 12-bit Plus Sign  
Offset  
•
•
Programmable tAD Adjust Feature  
1:1 Non-demuxed or 1:2 Demuxed LVDS  
Outputs  
•
•
•
AutoSync Feature for Multi-Chip Systems  
Single 1.9V ± 0.1V Power Supply  
292-Ball BGA Package (27mm x 27mm x  
2.4mm with 1.27mm Ball-Pitch); No Heat Sink  
Required  
Dissipating  
a typical 2.77/3.59 Watts in Non-  
Demultiplex Mode at 1.0/1.5 GSPS from a single  
1.9V supply, this device is specified to have no  
missing codes over the full operating temperature  
range.  
APPLICATIONS  
•
•
•
Wideband Communications  
Data Acquisition Systems  
Digital Oscilloscopes  
Each channel has its own independent DDR Data  
Clock, DCLKI and DCLKQ, which are in phase when  
both channels are powered up, so that only one Data  
Clock could be used to capture all data, which is sent  
out at the same rate as the input sample clock. If the  
1:2 Demux Mode is selected, a second 10-bit LVDS  
bus becomes active for each channel, such that the  
output data rate is sent out two times slower to relax  
data-capture timing requirements. The part can also  
be used as a single 2.0/3.0 GSPS ADC to sample  
one of the I or Q inputs. The output formatting can be  
programmed to be offset binary or two's complement  
and the Low Voltage Differential Signaling (LVDS)  
digital outputs are compatible with IEEE 1596.3-1996,  
with the exception of an adjustable common mode  
voltage between 0.8V and 1.2V to allow for power  
reduction for well-controlled back planes.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008–2013, Texas Instruments Incorporated  
1234567...83

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ADC10D1500CIUT 替代型号

型号 品牌 替代类型 描述 数据表
ADC10D1500CIUT/NOPB TI

类似代替

 10 位、双路 1.5GSPS 或单路 3.0GSPS 模数转换器 (ADC) | NXA

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