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ADC10D1000CCMLS

更新时间： 2024-11-25 06:36:19

品牌	Logo	应用领域
美国国家半导体 - NSC		转换器模数转换器
页数	文件大小	规格书
64页	2921K
描述
Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/DConverter

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技术参数
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ADC10D1000CCMLS 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	28.20 X 28.20 MM, 3.10 MM HEIGHT, 1.27 MM PITCH, CERAMIC, CCGA-376	Reach Compliance Code：	not_compliant
ECCN代码：	3A001.A.2.C	HTS代码：	8542.39.00.01
风险等级：	5.41	Is Samacsys：	N
最大模拟输入电压：	2.15 V	最小模拟输入电压：
最长转换时间：	0.001 µs	转换器类型：	ADC, PROPRIETARY METHOD
JESD-30 代码：	S-CBGA-B376	JESD-609代码：	e0
长度：	27.94 mm	最大线性误差 (EL)：	0.1367%
湿度敏感等级：	1	模拟输入通道数量：	1
位数：	10	功能数量：	1
端子数量：	376	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出位码：	OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式：	PARALLEL, WORD	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	BGA	封装等效代码：	PGA376(UNSPEC)
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	260	电源：	1.9 V
认证状态：	Not Qualified	采样速率：	2000 MHz
采样并保持/跟踪并保持：	TRACK	筛选级别：	MIL-STD-883
座面最大高度：	3.5 mm	子类别：	Analog to Digital Converters
标称供电电压：	1.9 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	40	宽度：	27.94 mm
Base Number Matches：	1

ADC10D1000CCMLS 数据手册

May 10, 2010

ADC10D1000QML

Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D

Converter

1.0 General Description

2.0 Features

The ADC10D1000 is the latest advance in National's Ultra-

High-Speed ADC family of products. This low-power, high-

performance CMOS analog-to-digital converter digitizes sig-

nals at 10-bit resolution at sampling rates of up to 1.0 GSPS

in dual channel mode or 2.0 GSPS in single channel mode.

The ADC10D1000 achieves excellent accuracy and dynamic

performance while consuming a typical 2.9 Watts of power.

This space grade, Radiation Tolerant part is rad hard to a

single event latch up level of greater than 120MeV and a total

dose (TID) of 100 krad(Si). The product is packaged in a her-

matic 376 column thermally enhanced CCGA package rated

over the temperature range of -55°C to +125°C.

Total Ionizing Dose

100 krad(Si)

120 Mev-cm²/mg

■

Single Event Latch-up

Excellent accuracy and dynamic performance

Low power consumption

■

R/W SPI Interface for Extended Control Mode

Internally terminated, buffered, differential analog inputs

Ability to interleave the two channels to operate one

channel at twice the conversion rate

Test patterns at output for system debug

■

Programmable 15-bit gain and 12-bit plus sign offset

adjustments

The ADC10D1000 builds upon the features, architecture and

functionality of the 8-bit GHz family of ADCs. New features

include an auto-sync feature for multi-chip synchronization,

independent programmable15-bit gain and 12-bit offset ad-

justment per channel, LC tank filter on the clock input, and the

option of two's complement format for the digital output data.

The unique folding and interpolating architecture, the fully dif-

ferential comparator design, the innovative design of the in-

ternal track-and-hold amplifier and the self-calibration

scheme enable a very flat response of all dynamic parameters

beyond Nyquist, producing a high 8.9 Effective Number of Bits

(ENOB) with a 498 MHz input signal and a 1.0 GHz sample

rate while providing a 10⁻¹⁸Code Error Rate (C.E.R.) Con-

suming a typical 2.9 Watts in Non-Demultiplex Mode at 1.0

GSPS from a single 1.9 Volt supply, this device is guaranteed

to have no missing codes over the full operating temperature

range.

Option of 1:2 demuxed or 1:1 non-demuxed LVDS outputs

Auto-sync feature for multi-chip systems

Single 1.9V±0.1V power supply

■

376 Ceramic Column Grid Array package (28.2mm x

28.2mm x 3.1mm with 1.27mm ball-pitch)

3.0 Key Specifications

(Non-Demux Non-DES Mode, Fs = 1.0 GSPS, Fin = 248 MHz)

Resolution

10 Bits

■

Conversion Rate

Dual channels at 1.0 GSPS (typ)

Single channel at 2.0 GSPS (typ)

Code Error Rate

—

10 ⁻¹⁸(typ)

9.0 bits (typ)

56.1 dBc (typ)

63 dBc (typ)

■

ENOB

SNR

SFDR

Each channel has its own independent DDR Data Clock,

DCLKI and DCLKQ, which are in phase when both channels

are powered up, so that only one Data Clock could be used

to capture all data, which is sent out at the same rate as the

input sample clock. If the 1:2 Demultiplexed Mode is selected,

a second 10-bit LVDS bus becomes active for each channel,

such that the output data rate is sent out two times slower, but

two times wider to relax data-capture timing margin. The two

channels (I and Q) can also be interleaved (DES Mode) and

used as a single 2.0 GSPS ADC to sample on the Q input.

The output formatting is offset binary or two's complement

and the Low Voltage Differential Signaling (LVDS) digital out-

puts are compatible with IEEE 1596.3-1996, with the excep-

tion of an adjustable common mode voltage between 0.8V

and 1.2V.

Full Power Bandwidth

DNL

2.8 GHz (typ)

±0.2 LSB (typ)

Power Consumption

Single Channel Enabled

Dual Channels Enabled

Power Down Mode

1.64W (typ)

2.9W (typ)

6 mW (typ)

—

4.0 Applications

Data Acquisition Systems

■

Wideband Communications

Direct RF Down Conversion

300718

www.national.com

12 3 4 5 6 7...64

中文翻译

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与ADC10D1000CCMLS相关器件

型号	品牌	获取价格	描述	数据表
ADC10D1000CCMPR	NSC	获取价格	Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/DConverter
ADC10D1000CCMPR	TI	获取价格	耐辐射加固保障 (RHA)、100krad、陶瓷、10 位、双通道 1GSPS 或单通道
ADC10D1000CCRQV	NSC	获取价格	Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/DConverter
ADC10D1000CIUT	NSC	获取价格	Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS ADC
ADC10D1000CIUT	TI	获取价格	10 位、双路 1.0GSPS 或单路 2.0GSPS 模数转换器 (ADC) \| NXA
ADC10D1000CIUT/NOPB	NSC	获取价格	Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS ADC
ADC10D1000CIUT/NOPB	TI	获取价格	10 位、双路 1.0GSPS 或单路 2.0GSPS 模数转换器 (ADC) \| NXA
ADC10D1000CVAL	NSC	获取价格	Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/DConverter
ADC10D1000NOPB	NSC	获取价格	Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC
ADC10D1000QML	NSC	获取价格	Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/DConverter

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