Datasheet > ADC1015S

ADC1015S

更新时间： 2024-11-01 06:36:19

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
39页	276K
描述
Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 01 - 12 April 2010 Preliminary data sheet

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ADC1015S 数据手册

ADC1015S series

Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps

with input buffer; CMOS or LVDS DDR digital outputs

Rev. 01 — 12 April 2010

Preliminary data sheet

1. General description

The ADC1015S is a single channel 10-bit Analog-to-Digital Converter (ADC) optimized for

high dynamic performances and low power consumption at sample rates up to 125 Msps.

Pipelined architecture and output error correction ensure the ADC1015S is accurate

enough to guarantee zero missing codes over the entire operating range. Supplied from a

single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,

thanks to a separate digital output supply.

The ADC1015S supports the Low Voltage Differential Signalling (LVDS) Double Data

Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the

user to easily configure the ADC.

The device also includes a SPI programmable full-scale to allow flexible input voltage

range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the

baseband to input frequencies of 170 MHz or more, the ADC1015S is ideal for use in

communications, imaging and medical applications - especially in high Intermediate

Frequency (IF) applications thanks to the integrated input buffer. The input buffer ensures

that the input impedance remains constant and low and the performance consistent over

a wide frequency range.

2. Features and benefits

SNR, 61.7 dBFS / SFDR, 86 dBc

Input bandwidth, 600 MHz

Power dissipation, 635 mW at 80 Msps,

including analog input buffer

SPI

Sample rate up to 125 Msps

10-bit pipelined ADC core

Clock input divider by 2 for less jitter

contribution

Duty cycle stabilizer

Integrated input buffer

Fast OuT of Range (OTR) detection

Flexible input voltage range: 1 V (p-p) to INL ±1.25 LSB, DNL ±0.25 LSB

2 V (p-p)

CMOS or LVDS DDR digital outputs

Offset binary, two’s complement, gray

code

Pin compatible with the ADC1415S

series, the ADC1215S series and the

ADC1115S125

Power-down and Sleep modes

HVQFN40 package

12 3 4 5 6 7...39

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与ADC1015S相关器件

型号	品牌	获取价格	描述	数据表
ADC1015S065HN/C1	NXP	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 01 - 12 April 2010 Prelimin
ADC1015S065HN-C1	IDT	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS
ADC1015S080HN/C1	NXP	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 01 - 12 April 2010 Prelimin
ADC1015S080HN-C1	IDT	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS
ADC1015S105HN/C1	NXP	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 01 - 12 April 2010 Prelimin
ADC1015S105HN-C1	IDT	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS
ADC1015S125HN/C1	NXP	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 01 - 12 April 2010 Prelimin
ADC1015S125HN-C1	IDT	获取价格	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS
ADC-101B	FARADAY	获取价格	VIDEO FRONT-END MODULES
ADC101C021	TI	获取价格	ADC081C021/ADC081C027 I2C-Compatible, 8-Bit Analog-to-Digital Converter with Alert

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