ADC10065
www.ti.com
SNAS225H –JULY 2003–REVISED APRIL 2013
ADC10065 10-Bit 65 MSPS 3V A/D Converter
Check for Samples: ADC10065
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FEATURES
DESCRIPTION
The ADC10065 is a monolithic CMOS analog-to-
digital converter capable of converting analog input
signals into 10-bit digital words at 65 Megasamples
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Single +3.0V Operation
Selectable 2 VP-P, 1.5 VP-P, or 1 VP-P Full-scale
Input
per second (MSPS). This converter uses
a
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400 MHz −3 dB Input Bandwidth
Low Power Consumption
Standby Mode
differential, pipeline architecture with digital error
correction and an on-chip sample-and-hold circuit to
provide a complete conversion solution, and to
minimize power consumption, while providing
excellent dynamic performance. A unique sample-
and-hold stage yields a full-power bandwidth of 400
MHz. Operating on a single 3.0V power supply, this
device consumes just 68.4 mW at 65 MSPS,
including the reference current. The Standby feature
reduces power consumption to just 14.1 mW.
On-Chip Reference and Sample-and-Hold
Amplifier
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Offset Binary or Two’s Complement Data
Format
Separate Adjustable Output Driver Supply to
Accommodate 2.5V and 3.3V Logic Families
The differential inputs provide a full scale selectable
input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the
possibility of a single-ended input. Full use of the
differential input is recommended for optimum
performance. An internal +1.2V precision bandgap
reference is used to set the ADC full-scale range, and
also allows the user to supply a buffered referenced
voltage for those applications requiring increased
accuracy. The output data format is user choice of
offset binary or two’s complement.
28-pin TSSOP Package
APPLICATIONS
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Ultrasound and Imaging
Instrumentation
Cellular Base Stations/Communications
Receivers
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Sonar/Radar
xDSL
This device is available in the 28-lead TSSOP
package and will operate over the industrial
temperature range of −40°C to +85°C.
Wireless Local Loops
Data Acquisition Systems
DSP Front Ends
KEY SPECIFICATIONS
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Resolution 10 Bits
Conversion Rate 65 MSPS
Full Power Bandwidth 400 MHz
DNL ±0.3 LSB (typ)
SNR (fIN = 11 MHz) 59.6 dB (typ)
SFDR (fIN = 11 MHz) −80 dB (typ)
Power Consumption, 65 MHz 68.4 mW
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated