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ADC0820CCJ PDF预览

ADC0820CCJ

更新时间: 2024-01-28 11:22:46
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器模数转换器
页数 文件大小 规格书
22页 475K
描述
8-Bit High Speed レP Compatible A/D Converter with Track/Hold Function

ADC0820CCJ 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:0.300 INCH, PLASTIC, DIP-20针数:20
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.02
Is Samacsys:N最大模拟输入电压:5.1 V
最小模拟输入电压:-0.1 V最长转换时间:2.5 µs
转换器类型:ADC, FLASH METHODJESD-30 代码:R-PDIP-T20
长度:26.695 mm最大线性误差 (EL):0.39%
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出位码:OFFSET BINARY
输出格式:PARALLEL, 8 BITS封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
座面最大高度:4.06 mm最大压摆率:15 mA
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

ADC0820CCJ 数据手册

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June 1999  
ADC0820  
8-Bit High Speed µP Compatible A/D Converter with  
Track/Hold Function  
General Description  
Features  
n Built-in track-and-hold function  
n No missing codes  
By using  
a half-flash conversion technique, the 8-bit  
ADC0820 CMOS A/D offers a 1.5 µs conversion time and  
dissipates only 75 mW of power. The half-flash technique  
consists of 32 comparators, a most significant 4-bit ADC and  
a least significant 4-bit ADC.  
n No external clocking  
n Single supply — 5 VDC  
n Easy interface to all microprocessors, or operates  
stand-alone  
n Latched TRI-STATE® output  
n Logic inputs and outputs meet both MOS and T2L  
voltage level specifications  
The input to the ADC0820 is tracked and held by the input  
sampling circuitry eliminating the need for an external  
sample-and-hold for signals moving at less than 100 mV/µs.  
For ease of interface to microprocessors, the ADC0820 has  
been designed to appear as a memory location or I/O port  
without the need for external interfacing logic.  
n Operates ratiometrically or with any reference value  
equal to or less than VCC  
n 0V to 5V analog input voltage range with single 5V  
supply  
Key Specifications  
n No zero or full-scale adjust required  
n Overflow output available for cascading  
n 0.3" standard width 20-pin DIP  
n 20-pin molded chip carrier package  
n 20-pin small outline package  
n Resolution  
8 Bits  
2.5 µs Max (RD Mode)  
1.5 µs Max (WR-RD Mode)  
75 mW Max  
n Conversion Time  
n Low Power  
n 20-pin shrink small outline package (SSOP)  
n Total Unadjusted  
1
±
±
2 LSB and 1 LSB  
Error  
Connection and Functional Diagrams  
Dual-In-Line, Small Outline  
and SSOP Packages  
Molded Chip Carrier  
Package  
DS005501-1  
DS005501-33  
Top View  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1999 National Semiconductor Corporation  
DS005501  
www.national.com  

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