Datasheet > ADC001

ADC001

更新时间： 2024-10-25 23:27:47

品牌	Logo	应用领域
其他 - ETC		转换器
页数	文件大小	规格书
2页	54K
描述
Analog to Digital Converter

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ADC001 数据手册

Delta Sigma A/D Converter

ADC001

14 bits resolution at 70 ksps (OSR=64)

•

Third order, single bit quantizer architecture in C5 (0.5µ) process

Differential input and reference reduce common mode effects

20mW input power at 5V

External voltage reference and decimation filter required

1.0 Description

A third-order, one-bit, Delta-Sigma modulator realized as a 2-1 cascade in the C5 process. The input and reference signals are

implemented differentially. Total input power is about 20mW at 5V. Integrators are correlated double sampled for low offset and

flicker noise. Reset switches are included for incremental ADC operation, in which the integrating capacitors are reset after a

number of samples equal to the Oversampling Ratio (OSR) have been accumulated.

2.0 Key Performance Features

Key Performance Features

Value

Voltage supply

5Volts+/-10%

4 mA max

+/- 1V

Operating current

Voltage reference span (Vref)

Input range

+/- 65% of Vref

5Mhz

Max clock rate

SINAD

80dB

Maximum resolution (at OSR=64)*

14 bits

*Requires external decimation filter

3.0 Block Diagram

SC Integrator

1 bit A/D

+Vref

–

1/2

∫

–

Reset

1/2

Reset

Control

1 bit D/A

1/4

-Vref

SC Integrator

1 bit A/D

Digital Differentiators

∫

–

+Vref

-Vref

Reset

1/2

1 bit D/A

Implemented in decimation filter (not incremental mode)

AMI Semiconductor

www.amis.com

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