ADAS1128

更新时间： 2024-02-06 07:00:29

品牌	Logo	应用领域
亚德诺 - ADI		转换器模数转换器
页数	文件大小	规格书
2页	75K
描述
128-Channel, 24-Bit Current-to-Digital ADC

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技术参数
数据手册

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ADAS1128 技术参数

生命周期：	Active	零件包装代码：	BGA
包装说明：	BGA,	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.81
转换器类型：	ADC, PROPRIETARY METHOD	JESD-30 代码：	S-PBGA-B
模拟输入通道数量：	1	位数：	24
功能数量：	1	输出位码：	BINARY
输出格式：	SERIAL	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	认证状态：	Not Qualified
采样速率：	0.0197 MHz	采样并保持/跟踪并保持：	SAMPLE
表面贴装：	YES	端子形式：	BALL
端子位置：	BOTTOM	Base Number Matches：	1

ADAS1128 数据手册

128-Channel, 24-Bit Current-to-Digital ADC

ADAS1128

FEATURES

GENERAL DESCRIPTION

128-channel, low level current-to-digital converter

Up to 24-bit resolution

Up to 19.7 kSPS (50.7 µs integration time)

Simultaneous sampling

Ultralow noise (down to 0.4 fC [2500e⁻])

User-adjustable full-scale range

INL: 0.025% of reading 0.75 ppm of FSR

Very low power dissipation: 4.5 mW/channel

LVDS self-clocked serial data interface

SPI configuration registers (daisy-chain)

On-board temperature sensor and reference buffer

10 mm × 10 mm, mini-BGA package

Low cost external components

The ADAS1128 is a 128-channel, current-to-digital, analog-to-

digital converter (ADC). It contains 128 low power, low noise,

low input current integrators, simultaneous sample-and-holds,

and two high speed, high resolution ADCs with configurable

sampling rate and resolutions up to 24 bits.

All converted channel results are output on a single LVDS self-

clocked serial interface, which reduces external hardware.

An SPI-compatible serial interface allows configuration of the

ADC using the SDI input. The SDO output allows the user to

daisy-chain several ADCs on a single, 3-wire bus. The ADAS1128

uses the separate supply IOVDD to reduce digital noise effect

on the conversions.

Support tools

Evaluation board

The ADAS1128 is in a 10 mm × 10 mm, mini-BGA package.

Reference design with reference layout

FPGA Verilog code

APPLICATIONS

Medical, industrial, and security CT scanner data acquisition

Photodiode sensors

Dosimetry and radiation therapy systems

Optical fiber power monitoring

X-ray detection systems

High channel-count data acquisition systems (current or

voltage inputs)

FUNCTIONAL BLOCK DIAGRAM

TO NEXT

SDI

2.5V 3.3V

TO ALL ADCs

BUFPL

BUFNL

SDO

SCK

REF

AN0

CONFIGURATION

SDI

S/H

RESET

OR0

–

ADCL

AN63

AN64

S/H

OR63

DOUTx

CLKx

SYNC

FPGA

LVDS/CMOS

INTERFACE

DATA

PROCESSING

OR[0:127]

2.5V

IOVDD

IOGND

OR64

VIO

TEMPERATURE

–

ADCH

ADAS1128

AN127

KGND

S/H

OR127

SDI

BUFPH

BUFNH

REF

SDI

FROM

2.048V

FROM DOUT

OF OTHER ADCs

SDO

Figure 1.

Rev. SpC

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

中文翻译

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