64-Channel, 24-Bit Current-to-Digital ADC
ADAS1127
FEATURES
GENERAL DESCRIPTION
64-channel, low level current-to-digital converter
Up to 24-bit resolution
Up to 19.7 kSPS (50.7 μs integration time)
Simultaneous sampling
Ultralow noise (down to 0.4 fC [2500e−])
User-adjustable full-scale range
INL: 0.025ꢀ of reading 0.75 ppm of FSR
Very low power dissipation: 6.25 mW/channel
LVDS self-clocked serial data interface
SPI configuration registers (daisy-chain)
The ADAS1127 is a 64-channel, current-to-digital, analog-to-
digital converter (ADC). It contains 64 low power, low noise,
low input current integrators, simultaneous sample-and-holds,
and a high speed, high resolution ADCs with configurable
sampling rate and resolutions up to 24 bits.
All converted channel results are output on a single LVDS self-
clocked serial interface, which reduces external hardware.
An SPI-compatible serial interface allows configuration of the
ADC using the SDI input. The SDO output allows the user to
On-board temperature sensor and reference buffer
10 mm × 10 mm, mini-BGA package
Low cost external components
Support tools
Evaluation board
Reference design with reference layout
FPGA Verilog code
daisy-chain several ADCs on a single, 3-wire bus. The
ADAS1127 uses the separate supply IOVDD to reduce the
digital noise effect on the conversions.
The ADAS1127 is in a 10 mm × 10 mm, mini-BGA package.
For more information on the ADAS1127, contact Analog
Devices, Inc, at adas@analog.com.
APPLICATIONS
Medical, industrial, and security CT scanner data acquisition
Photodiode sensors
Dosimetry and radiation therapy systems
Optical fiber power monitoring
X-ray detection systems
High channel-count data acquisition systems (current or
voltage inputs)
FUNCTIONAL BLOCK DIAGRAM
TO NEXT
SDI
2.5V
3.3V
TO ALL ADCs
SDO
SCK
CS
F
AN0
CONFIGURATION
SDI
S/H
RESET
OR0
F
AN31
S/H
OR31
DOUTx
CLKx
SYNC
FPGA
+
LVDS/CMOS
INTERFACE
DATA
PROCESSING
ADCL
–
F
AN32
S/H
OR[0:63]
2.5V
IOVDD
IOGND
OR32
VIO
TEMPERATURE
F
ADAS1127
AN63
S/H
OR63
SDI
KGND
BUFP
BUFN
REF
SDI
2.048V
FROM DOUT
OF OTHER ADCs
FROM
PREVIOUS
SDO
Figure 1.
Rev. Sp0
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