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AD9912ABCPZ-REEL7 PDF预览

AD9912ABCPZ-REEL7

更新时间: 2024-01-05 16:35:02
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
40页 649K
描述
1 GSPS Direct Digital Synthesizer with 14-Bit DAC

AD9912ABCPZ-REEL7 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.23
最大模拟输出电压:0.5 V最小模拟输出电压:-0.5 V
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:PARALLEL, WORDJESD-30 代码:S-XQCC-N64
JESD-609代码:e3长度:9 mm
湿度敏感等级:3位数:14
功能数量:1端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1 mm标称供电电压:1.8 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:9 mm
Base Number Matches:1

AD9912ABCPZ-REEL7 数据手册

 浏览型号AD9912ABCPZ-REEL7的Datasheet PDF文件第2页浏览型号AD9912ABCPZ-REEL7的Datasheet PDF文件第3页浏览型号AD9912ABCPZ-REEL7的Datasheet PDF文件第4页浏览型号AD9912ABCPZ-REEL7的Datasheet PDF文件第5页浏览型号AD9912ABCPZ-REEL7的Datasheet PDF文件第6页浏览型号AD9912ABCPZ-REEL7的Datasheet PDF文件第7页 
1 GSPS Direct Digital  
Synthesizer with 14-Bit DAC  
AD9912  
FEATURES  
APPLICATIONS  
1 GSPS internal clock speed (up to 400 MHz output directly)  
Integrated 1 GSPS 14-bit DAC  
48-bit frequency tuning word with 4 μHz resolution  
Differential HSTL comparator  
Flexible system clock input accepts either crystal or external  
reference clock  
Agile LO frequency synthesis  
Low jitter, fine tune clock generation  
Test and measurement equipment  
Wireless base stations and controllers  
Secure communications  
Fast frequency hopping  
On-chip low noise PLL REFCLK multiplier  
2 SpurKiller channels  
GENERAL DESCRIPTION  
Low jitter clock doubler for frequencies up to 750 MHz  
Single-ended CMOS comparator; frequencies of <150 MHz  
Programmable output divider for CMOS output  
Serial I/O control  
The AD9912 is a direct digital synthesizer (DDS) that features  
an integrated 14-bit digital-to-analog converter (DAC). The  
AD9912 features a 48-bit frequency tuning word (FTW) that  
can synthesize frequencies in step sizes no larger than 4 μHz.  
Absolute frequency accuracy can be achieved by adjusting the  
DAC system clock.  
Excellent dynamic performance  
Software controlled power-down  
Available in two 64-lead LFCSP packages  
Residual phase noise @ 250 MHz  
10 Hz offset: −113 dBc/Hz  
1 kHz offset: −133 dBc/Hz  
The AD9912 also features an integrated system clock phase-  
locked loop (PLL) that allows for system clock inputs as low  
as 25 MHz.  
100 kHz offset: −153 dBc/Hz  
40 MHz offset: −161 dBc/Hz  
The AD9912 operates over an industrial temperature range,  
spanning −40°C to +85°C.  
BASIC BLOCK DIAGRAM  
AD9912  
DAC_OUT  
STARTUP  
S1 TO S4  
CONFIGURATION  
LOGIC  
FILTER  
DIRECT  
FDBK_IN  
DIGITAL  
SYNTHESIS  
CORE  
OUT  
CLOCK  
OUTPUT  
DRIVERS  
DIGITAL  
INTERFACE  
SERIAL PORT,  
I/O LOGIC  
OUT_CMOS  
SYSTEM CLOCK  
MULTIPLIER  
Figure 1.  
Rev. F  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.  
 
 
 

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