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AD9864BCPZ

更新时间: 2024-11-08 23:16:19
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亚德诺 - ADI 电信集成电路电信电路PC
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44页 1734K
描述
IF Digitizing Subsystem

AD9864BCPZ 数据手册

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IF Digitizing Subsystem  
AD9864*  
PRODUCT OVERVIEW  
FEATURES  
The AD9864 is a general-purpose IF subsystem that digitizes a  
low level 10 MHz to 300 MHz IF input with a signal bandwidth  
ranging from 6.8 kHz to 270 kHz. The signal chain of the  
AD9864 consists of a low noise amplifier (LNA), a mixer, a  
band-pass Σ-∆ analog-to-digital converter (ADC), and a deci-  
mation filter with programmable decimation factor. An auto-  
matic gain control (AGC) circuit gives the AD9864 12 dB of  
continuous gain adjustment. Auxiliary blocks include both  
clock and LO synthesizers.  
10 MHz to 300 MHz input frequency  
6.8 kHz to 270 kHz output signal bandwidth  
7.5 dB SSB NF  
–7.0 dBm IIP3  
AGC free range up to –34 dBm  
12 dB continuous AGC range  
16 dB front end attenuator  
Baseband I/Q 16-bit (or 24-bit) serial digital output  
LO and sampling clock synthesizers  
Programmable decimation factor, output format,  
AGC, and sythesizer settings  
370 input impedance  
The high dynamic range of the AD9864 and inherent antialias-  
ing provided by the band-pass Σ-∆ converter allow the device to  
cope with blocking signals up to 95 dB stronger than the desired  
signal. This attribute often reduces the cost of a radio by reduc-  
ing IF filtering requirements. Also, it enables multimode radios  
of varying channel bandwidths, allowing the IF filter to be  
specified for the largest channel bandwidth.  
2.7 V to 3.6 V supply voltage  
Low current consumption: 17 mA  
48-lead LFCSP package  
APPLICATIONS  
The SPI® port programs numerous parameters of the AD9864,  
allowing the device to be optimized for any given application.  
Programmable parameters include synthesizer divide ratios,  
AGC attenuation and attack/decay time, received signal  
strength level, decimation factor, output data format, 16 dB  
attenuator, and the selected bias currents.  
Multimode narrow-band radio products  
Analog/digital UHF/VHF FDMA receivers  
TETRA, APCO25, GSM/EDGE  
Portable and mobile radio products  
SATCOM terminals  
The AD9864 is available in a 48-lead LFCSP package and  
operates from a single 2.7 V to 3.6 V supply. The total power  
consumption is typically 56 mW and a power-down mode is  
provided via serial interfacing.  
*Protected by U.S. Patent No. 5,969,657; other patents pending.  
FUNCTIONAL BLOCK DIAGRAM  
MXOP MXON IF2P IF2N  
GCP GCN  
DAC  
AGC  
AD9864  
–16dB  
LNA  
DECIMATION  
FILTER  
-ADC  
FORMATTING/SSI  
DOUTA  
DOUTB  
IFIN  
FS  
CLKOUT  
FREF  
CONTROL LOGIC  
LO  
VOLTAGE  
CLK SYN  
SYN  
REFERENCE  
SPI  
IOUTL  
LOP LON  
IOUTC CLKP  
LOOP FILTER  
CLKN VREFP VCM VREFN PC PD PE  
SYNCB  
LO VCO AND  
LOOP FILTER  
Figure 1. AD9864 Block Diagram  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2003 Analog Devices, Inc. All rights reserved.  

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