12-Bit, 125 MSPS
®
a
Dual TxDAC+ D/A Converter
AD97651
FEATURES
FUNCTIONAL BLOCK DIAGRAM
12-Bit Dual Transmit DAC
125 MSPS Update Rate
DVDD DCOM AVDD ACOM
CLK1
Excellent SFDR to Nyquist @ 5 MHz Output: 75 dBc
Excellent Gain and Offset Matching: 0.1%
Fully Independent or Single Resistor Gain Control
Dual Port or Interleaved Data
On-Chip 1.2 V Reference
Single 5 V or 3 V Supply Operation
Power Dissipation: 380 mW @ 5 V
Power-Down Mode: 50 mW @ 5 V
48-Lead LQFP
I
I
OUTA1
“1”
“1”
PORT1
LATCH
DAC
OUTB1
REFIO
FSADJ1
FSADJ2
GAINCTRL
REFERENCE
WRT1
WRT2
DIGITAL
AD9765
INTERFACE
BIAS
GENERATOR
SLEEP
I
I
OUTA2
“2”
LATCH
“2”
DAC
PORT2
OUTB2
APPLICATIONS
MODE
CLK2
Communications
Base Stations
Digital Synthesis
Quadrature Modulation
and provide a nominal full-scale current of 20 mA. The full-
scale currents between each DAC are matched to within 0.1%.
PRODUCT DESCRIPTION
The AD9765 is a dual port, high speed, two channel, 12-bit
CMOS DAC. It integrates two high quality 12-bit TxDAC+
cores, a voltage reference and digital interface circuitry into a small
48-lead LQFP package. The AD9765 offers exceptional ac and
dc performance while supporting update rates up to 125 MSPS.
The AD9765 is manufactured on an advanced low cost CMOS
process. It operates from a single supply of 3.0 V to 5.0 V and
consumes 380 mW of power.
PRODUCT HIGHLIGHTS
1. The AD9765 is a member of a pin-compatible family of dual
TxDACs providing 8-, 10-, 12-, and 14-bit resolution.
The AD9765 has been optimized for processing I and Q data in
communications applications. The digital interface consists of
two double-buffered latches as well as control logic. Separate
write inputs allow data to be written to the two DAC ports
independent of one another. Separate clocks control the update
rate of the DACs.
2. Dual 12-Bit, 125 MSPS DACs: A pair of high performance
DACs optimized for low distortion performance provide for
flexible transmission of I and Q information.
A mode control pin allows the AD9765 to interface to two separate
data ports, or to a single interleaved high speed data port. In inter-
leaving mode the input data stream is demuxed into its original
I and Q data and then latched. The I and Q data is then con-
verted by the two DACs and updated at half the input data rate.
3. Matching: Gain matching is typically 0.1% of full scale, and
offset error is better than 0.02%.
4. Low Power: Complete CMOS Dual DAC function operates
on 380 mW from a 3.0 V to 5.0 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
The GAINCTRL pin allows two modes for setting the full-scale
current (IOUTFS) of the two DACs. IOUTFS for each DAC can be
set independently using two external resistors, or IOUTFS for both
DACs can be set by using a single external resistor.2
5. On-Chip Voltage Reference: The AD9765 includes a 1.20 V
temperature-compensated bandgap voltage reference.
6. Dual 12-Bit Inputs: The AD9765 features a flexible dual-
port interface allowing dual or interleaved input data.
The DACs utilize a segmented current source architecture com-
bined with a proprietary switching technique to reduce glitch
energy and to maximize dynamic accuracy. Each DAC provides
differential current output thus supporting single-ended or dif-
ferential applications. Both DACs can be simultaneously updated
TxDAC+ is a registered trademark of Analog Devices, Inc.
1Patent pending.
2Please see GAINCTRL Mode section, for important date code information on
this feature.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
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