14-Bit, 80 MSPS/155 MSPS, 1.8 V
Serial Output Analog-to-Digital Converter (ADC)
Data Sheet
AD9641
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
SDIO SCLK CSB
DRVDD
JESD204A coded serial digital outputs
SNR = 73.7 dBFS at 70 MHz/80 MSPS
SPI
AD9641
SNR = 72.8 dBFS at 70 MHz and 155 MSPS
SFDR = 94 dBc at 70 MHz and 80 MSPS
SFDR = 90 dBc at 70 MHz and 155 MSPS
Low power: 238 mW at 80 MSPS, 313 mW at 155 MSPS
1.8 V supply operation
PROGRAMMING DATA
ADC
DOUT+
DOUT–
DSYNC+
DSYNC–
VIN+
VIN–
VCM
Integer 1-to-8 input clock divider
IF sampling frequencies to 250 MHz
REFERENCE
DATA RATE
MULTIPLIER
−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS
−148.1 dBFS/Hz input noise at 180 MHz and 155 MSPS
Programmable internal ADC voltage reference
Flexible analog input range: 1.4 V p-p to 2.1 V p-p
ADC clock duty cycle stabilizer (DCS)
DUTY CYCLE
STABILIZER
CLK+
CLK–
DIVIDE-BY-1
MULTICHIP
SYNC
TO
DIVIDE-BY-8
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
AGND
SYNC
PDWN
DRGND
Figure 1.
APPLICATIONS
The ADC output data is routed directly to the JESD204A serial
output port. This output is at CML voltage levels. A CMOS or
LVDS synchronization input (DSYNC) is provided.
Communications
Diversity radio systems
Multimode digital receivers (3G and 4G)
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
The flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface.
The AD9641 is available in a 32-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.
This product is protected by a U.S. patent.
GENERAL DESCRIPTION
The AD9641 is a 14-bit, 80 MSPS/155 MSPS analog-to-digital
converter (ADC) with a high speed serial output interface. The
AD9641 is designed to support communications applications
where high performance, combined with low cost, small size, and
versatility, is desired. The JESD204A high speed serial interface
reduces board routing requirements and lowers pin count
requirements for the receiving device.
PRODUCT HIGHLIGHTS
1. An on-chip PLL allows users to provide a single ADC
sampling clock. The PLL multiplies the ADC sampling clock
to produce the corresponding JESD204A data rate clock.
2. The configurable JESD204A output block coded data rate
supports up to 1.6 Gbps.
3. A proprietary differential input maintains excellent SNR
performance for input frequencies of up to 250 MHz.
4. Operation is from a single 1.8 V power supply.
5. The standard serial port interface (SPI) supports various
product features and functions, such as data formatting
(offset binary, twos complement, or Gray coding), control-
ling the clock DCS, power-down, test modes, voltage
reference mode, and serial output configuration.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth, differential sample-and-hold,
analog input amplifiers that support a variety of user-selectable
input ranges. An integrated voltage reference eases the design
considerations. A duty cycle stabilizer (DCS) is provided to
compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance.
Rev. B
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