12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS,
1.3 V/2.5 V Analog-to-Digital Converter
Data Sheet
AD9625
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD DRGND
12-bit 2.5 GSPS ADC, no missing codes
SFDR = 79 dBc, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS
SFDR = 77 dBc, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS
SNR = 57.6 dBFS, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS
SNR = 57 dBFS, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS
Noise spectral density = −149.5 dBFS/Hz at 2.5 GSPS
Differential analog input: 1.2 V p-p
REFERENCE
DIGITAL INTERFACE
AND CONTROL
SERDOUT[0]±
SERDOUT[1]±
SERDOUT[2]±
SERDOUT[3]±
SERDOUT[4]±
SERDOUT[5]±
SERDOUT[6]±
SERDOUT[7]±
VCM
VIN+
VIN–
DDC
fS/8 OR fS/16
ADC
CORE
RBIAS_EXT
FD
CMOS
DIGITAL
INPUT/
CONTROL
REGISTERS
Differential clock input
RSTB
IRQ
OUTPUT
3.2 GHz analog input bandwidth, full power
High speed 6- or 8-lane JESD204B serial output at 2.6 GSPS
Subclass 1: 6.5 Gbps at 2.6 GSPS
Two independent decimate by 8 or decimate by 16 filters
with 10-bit NCOs
SYSREF±
CLK±
LVDS
DIGITAL
INPUT/
CLOCK
MANAGEMENT
SYNCINB±
DIVCLK±
OUTPUT
CMOS DIGITAL
INPUT/OUTPUT
AD9625
Supply voltages: 1.3 V, 2.5 V
SDIO SCLK CSB
Serial port control
Flexible digital output modes
Figure 1.
Built-in selectable digital test patterns
Timestamp feature
Conversion error rate < 10−15
APPLICATIONS
Spectrum analyzers
Military communications
Radar
High performance digital storage oscilloscopes
Active jamming/antijamming
Electronic surveillance and countermeasures
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9625 is a 12-bit monolithic sampling analog-to-digital
converter (ADC) that operates at conversion rates of up to
2.6 giga samples per second (GSPS). This product is designed
for sampling wide bandwidth analog signals up to the second
Nyquist zone. The combination of wide input bandwidth, high
sampling rate, and excellent linearity of the AD9625 is ideally
suited for spectrum analyzers, data acquisition systems, and a
wide assortment of military electronics applications, such as
radar and electronic countermeasures.
1. High performance: exceptional SFDR in high sample rate
applications, direct RF sampling, and on-chip reference.
2. Flexible digital data output formats based on the JESD204B
specification.
3. Control path SPI interface port that supports various
product features and functions, such as data formatting,
gain, and offset calibration values.
The analog input, clock, and SYSREF signals are differential
inputs. The JESD204B-based high speed serialized output is
configurable in a variety of one-, two-, four-, six-, or eight-lane
configurations. The product is specified over the industrial
temperature range of −40°C to +85°C, measured at the case.
Rev. C
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