10-Bit, 105 MSPS/125 MSPS/150 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9600
I/Q demodulation systems
Smart antenna systems
Digital predistortion
FEATURES
SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS
SFDR = 81 dBc to 70 MHz at 150 MSPS
Low power: 825 mW at 150 MSPS
General-purpose software radios
Broadband data applications
Data acquisition
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply
Integer 1 to 8 input clock divider
Nondestructive testing
Intermediate frequency (IF) sampling frequencies up to 450 MHz
Internal analog-to-digital converter (ADC) voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input: 1 V p-p to 2 V p-p range
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes
PRODUCT HIGHLIGHTS
1. Integrated dual, 10-bit, 150 MSPS/125 MSPS/105 MSPS ADC.
2. Fast overrange detect and signal monitor with serial output.
3. Signal monitor block with dedicated serial output mode.
4. Proprietary differential input maintains excellent SNR
performance for input frequencies up to 450 MHz.
5. The AD9600 operates from a single 1.8 V supply and
features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
6. A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or gray coding), enabling the
clock DCS, power-down mode, and voltage reference mode.
7. The AD9600 is pin compatible with the AD9627-11, AD9627,
and AD9640, allowing a simple migration from 10 bits to
11 bits, 12 bits, or 14 bits.
Integrated receive features
Fast detect/threshold bits
Composite signal monitor
APPLICATIONS
Point-to-point radio receivers (GPSK, QAM)
Diversity radio systems
FUNCTIONAL BLOCK DIAGRAM
SDIO/ SCLK/
DCS DFS CSB DRVDD
AVDD DVDD
FD[0:3]A
FD BITS/THRESHOLD
DETECT
SPI
AD9600
D9A
D0A
PROGRAMMING DATA
VIN + A
VIN – A
SHA
ADC
CLK+
CLK–
–
+
DIVIDE 1
TO 8
VREF
SENSE
SIGNAL
MONITOR
DCOA
DCOB
CML
REFERENCE
SELECT
DUTY CYCLE
STABLIZER
DCO
GENERATION
VIN – B
VIN + B
ADC
SHA
D9B
D0B
SERIAL MONITOR
DATA
MULTICHIP
SYNC
FD BITS/THRESHOLD
DETECT
SERIAL MONITOR
INTERFACE
AGND SYNC
NOTES
FD[0:3]B
SMI
SMI
SMI
DRGND
SDFS SCLK/ SDO/
PDWN OEB
1.PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
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