16-Channel, 125 MHz Bandwidth, JESD204B
Analog-to-Digital Converter
Data Sheet
AD9083
FEATURES
APPLICATIONS
1.0 V and 1.8 V supply operation
125 MHz usable analog input bandwidth
Sample rate up to 2 GSPS
Noise spectral density in 100 MHz bandwidth =
−145 dBFS/Hz, 2.0 GSPS encode
SNR = 66 dBFS in 100 MHz bandwidth, 2.0 GSPS encode
SNR = 82 dBFS in 15.625 MHz bandwidth, 2.0 GSPS encode
SFDR = 60 dBc in 100 MHz bandwidth, 2.0 GSPS encode
SFDR = 80 dBc in 15.625 MHz bandwidth, 2.0 GSPS encode
90 mW total power per channel at 2.0 GSPS (default settings)
Flexible input range: 0.5 V p-p to 2 V p-p differential
90 dB channel crosstalk, 2.0 GSPS encode
Digital processor
Millimeter wave imaging
Electronic beam forming and phased arrays
Multichannel wideband receivers
Electronic support measures
PRODUCT HIGHLIGHTS
1. Continuous time, Σ-Δ analog-to-digital converters (ADCs)
support signal bandwidths of up to 125 MHz with low
power and minimal filtering.
2. Integrated digital processing blocks reduce data payload
and lower overall system cost.
3. Configurable JESD204B interface reduces printed circuit
board (PCB) complexity.
4. Flexible power-down options.
CIC decimation filter
5. SPI interface controls various product features and
functions to meet specific system requirements.
6. Small, 9 mm × 9 mm, 100-ball CSP_BGA package, simple
interface, and integrated digital processing save PCB space.
Programmable DDC
Data gating
JESD204B Subclass 1 encoded outputs
Supports up to 16 Gbps/lane
Flexible sample data processing
Flexible JESD204B lane configurations
Large signal dither
Serial port control
FUNCTIONAL BLOCK DIAGRAM
AVDD
(1V)
AVDD1P8
(1.8V)
DVDD
(1V)
DVDD1P8
(1.8V)
AD9083
NCO
NCO
NCO
2
0
1
DECIMATE
BY J
GAIN
VIN1+ TO
VIN16+
MIXER
AVERAGING AND
DECIMATION FILTER
ADC
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
VIN1– TO
VIN16–
CIC DECIMATOR
JESD204B
OUTPUTS
AVERAGING AND
MIXER
MIXER
GAIN
GAIN
DECIMATION FILTER
AVERAGING AND
DECIMATION FILTER
SYNCINB±
16 CHANNELS
CLK±
CSB
PLL,
SPI AND CONTROL
REGISTERS
SYSREF±
TRIG±
JESD204B SUBCLASS1 CONTROL,
AND CLOCK DISTRIBUTION
SCLK
SDIO
AGND
DGND
PD/STBY
Figure 1.
Rev. 0
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