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AD8152JBP PDF预览

AD8152JBP

更新时间: 2024-01-05 11:03:06
品牌 Logo 应用领域
亚德诺 - ADI 开关
页数 文件大小 规格书
32页 1210K
描述
34 x 34, 3.2 Gbps Asynchronous Digital Crosspoint Switch

AD8152JBP 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:BGA
包装说明:LBGA,针数:256
Reach Compliance Code:unknown风险等级:5.44
Is Samacsys:N模拟集成电路 - 其他类型:CROSS POINT SWITCH
JESD-30 代码:S-PBGA-B256JESD-609代码:e1
长度:27 mm湿度敏感等级:3
信道数量:34功能数量:1
端子数量:256最大通态电阻 (Ron):57 Ω
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
峰值回流温度(摄氏度):260座面最大高度:1.7 mm
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.25 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:OTHER端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:40
宽度:27 mmBase Number Matches:1

AD8152JBP 数据手册

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34 
؋
 34, 3.2 Gbps  
a
Asynchronous Digital Crosspoint Switch  
AD8152*  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Low Cost  
Low Power  
VCC  
2.0 W @ 2.5 V (Outputs Enabled)  
<100 mW @ 2.5 V (Outputs Disabled)  
34 
؋
 34, Fully Differential, Nonblocking Array  
3.2 Gbps per Port NRZ Data Rate  
Wide Power Supply Range: 2.5 V to 3.3 V  
LVTTL or LVCMOS Level Control Inputs:  
@ 2.5 V to 3.3 V  
34  
34  
34  
34  
INP  
OUTP  
VTTO  
34 
؋
 34  
DIFFERENTIAL  
SWITCH MATRIX  
OUTPUT  
LEVEL  
DACs  
VTTI  
OUTN  
INN  
Low Jitter: 45 ps  
MATRIX  
CONNECTION  
LATCHES  
CONNECTION  
DECODE  
D[5:0]  
Drives a Backplane Directly  
Programmable Output Swing  
100 mV to 1.6 V Differential  
50 On-Chip I/O Termination  
User Controlled Voltage at the Load  
Minimizes Power Dissipation  
Dual Rank Latches  
OUTPUT  
LEVEL  
LATCHES  
RESET  
CS  
A[6:0]  
RE  
CONTROL  
LOGIC  
WE  
Available in 256-Ball Grid Array  
AD8152  
UPDATE  
APPLICATIONS  
Fiber Optic Network Switching  
High Speed Serial Backplane Routing to OC-48 with FEC  
Gigabit Ethernet  
VEE  
Digital Video (HDTV)  
Data Storage Networks  
GENERAL DESCRIPTION  
AD8152 is a member of the Xstream line of products and is a  
breakthrough in digital switching, offering a large switch array  
(34 × 34) on very little power, typically 2.0 W. Additionally, it  
operates at data rates up to 3.2 Gbps per port, making it suitable  
for Sonet/SDH OC-48 with Forward Error Correction (FEC).  
The AD8152’s useful supply voltage range allows the user to  
operate at LVPECL/CML data levels down to 2.5 V. The control  
interface is LVTTL or LVCMOS compatible on 2.5 V to 3.3 V.  
The AD8152’s fully differential signal path reduces jitter and  
crosstalk while allowing the use of smaller single-ended voltage  
swings. It is offered in a 256-ball SBGA package that operates  
over the industrial temperature range of 0°C to 85°C.  
80ps/DIV  
Figure 1. Eye Pattern, 3.2 Gbps, PRBS 23  
*Patent Pending  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© 2003 Analog Devices, Inc. All rights reserved.  

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