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AD800-45BQ

更新时间： 2024-11-23 22:05:23

品牌	Logo	应用领域
亚德诺 - ADI		时钟
页数	文件大小	规格书
12页	255K
描述
Clock Recovery and Data Retiming Phase-Locked Loop

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AD800-45BQ 数据手册

Clock Recovery and Data Retiming

Phase-Locked Loop

AD800/AD802*

FUNCTIO NAL BLO CK D IAGRAM

FEATURES

Standard Products

44.736 Mbps—DS-3

51.84 Mbps—STS-1

155.52 Mbps—STS-3 or STM-1

Accepts NRZ Data, No Pream ble Required

Recovered Clock and Retim ed Data Outputs

Phase-Locked Loop Type Clock Recovery—No Crystal

Required

Random J itter: 20؇ Peak-to-Peak

Pattern J itter: Virtually Elim inated

10KH ECL Com patible

COMPENSATING

ZERO

LOOP

DATA

INPUT

DET

∑

FILTER

VCO

RECOVERED

CLOCK

OUTPUT

DET

RETIMED

DATA

OUTPUT

RETIMING

DEVICE

Single Supply Operation: –5.2 V or +5 V

Wide Operating Tem perature Range: –40؇C to +85؇C

AD800/AD802

FRAC

OUTPUT

P RO D UCT D ESCRIP TIO N

During the process of acquisition the frequency detector

provides a Frequency Acquisition (FRAC) signal which

indicates that the device has not yet locked onto the input data.

T his signal is a series of pulses which occur at the points of cycle

slip between the input data and the synthesized clock signal.

Once the circuit has acquired frequency lock no pulses occur at

the FRAC output.

T he AD800 and AD802 employ a second order phase-locked

loop architecture to perform clock recovery and data retiming

on Non-Return to Zero, NRZ, data. T his architecture is

capable of supporting data rates between 20 Mbps and 160

Mbps. T he products described here have been defined to work

with standard telecommunications bit rates. 45 Mbps DS-3 and

52 Mbps ST S-1 are supported by the AD800-45 and

AD800-52 respectively. 155 Mbps ST S-3 or ST M-1 are

supported by the AD802-155.

T he inclusion of a precisely trimmed VCO in the device

eliminates the need for external components for setting center

frequency, and the need for trimming of those components. T he

VCO provides a clock output within ±20% of the device center

frequency in the absence of input data.

Unlike other PLL-based clock recovery circuits, these devices

do not require a preamble or an external VCXO to lock onto

input data. T he circuit acquires frequency and phase lock using

two control loops. T he frequency acquisition control loop

initially acquires the clock frequency of the input data. T he

phase-lock loop then acquires the phase of the input data, and

ensures that the phase of the output signals track changes in the

phase of the input data. T he loop damping of the circuit is

dependent on the value of a user selected capacitor; this defines

jitter peaking performance and impacts acquisition time. T he

devices exhibit 0.08 dB jitter peaking, and acquire lock on

random or scrambled data within 4 × 10⁵bit periods when

using a damping factor of 5.

T he AD800 and AD802 exhibit virtually no pattern jitter, due

to the performance of the patented phase detector. T otal loop

jitter is 20° peak-to-peak. Jitter bandwidth is dictated by mask

programmable fractional loop bandwidth. T he AD800, used for

data rates < 90 Mbps, has been designed with a nominal loop

bandwidth of 0.1% of the center frequency. T he AD802, used

for data rates in excess of 90 Mbps, has a loop bandwidth of

0.08% of center frequency.

All of the devices operate with a single +5 V or –5.2 V supply.

*P r otected by U.S. P atent No. 5,027,085.

REV. B

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

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AD8004AR-14	ADI	获取价格	Quad 3000 V/us, 35 mW Current Feedback Amplifier
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