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AD7910ARMZ2 PDF预览

AD7910ARMZ2

更新时间: 2024-11-20 12:32:59
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 493K
描述
250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70

AD7910ARMZ2 数据手册

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250 kSPS,  
10-/12-Bit ADCs in 6-Lead SC70  
AD7910/AD7920  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
Throughput rate: 250 kSPS  
V
DD  
Specified for VDD of 2.35 V to 5.25 V  
Low power  
3.6 mW typ at 250 kSPS with 3 V supplies  
12.5 mW typ at 250 kSPS with 5 V supplies  
Wide input bandwidth  
10-/12-BIT  
SUCCESSIVE  
APPROXIMATION  
ADC  
V
IN  
T/H  
71 dB SNR at 100 kHz input frequency  
Flexible power/serial clock speed management  
No pipeline delays  
High speed serial interface  
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible  
Standby mode: 1 μA max  
SCLK  
SDATA  
CS  
CONTROL LOGIC  
AD7910/AD7920  
6-lead SC70 package  
8-lead MSOP package  
GND  
Figure 1.  
APPLICATIONS  
Battery-powered systems  
Personal digital assistants  
Medical instruments  
Mobile communications  
Instrumentation and control systems  
Data acquisition systems  
High speed modems  
Optical sensors  
GENERAL DESCRIPTION  
PRODUCT HIGHLIGHTS  
The AD7910/AD79201 are, respectively, 10-bit and 12-bit, high  
speed, low power, successive approximation ADCs. The parts  
operate from a single 2.35 V to 5.25 V power supply and feature  
throughput rates up to 250 kSPS. The parts contain a low noise,  
wide bandwidth track-and-hold amplifier that can handle input  
frequencies in excess of 13 MHz.  
1. 10-/12-bit ADCs in SC70 and MSOP packages.  
2. Low power consumption.  
3. Flexible power/serial clock speed management. The  
conversion rate is determined by the serial clock, allowing  
the conversion time to be reduced through the serial clock  
speed increase. This allows the average power consumption  
to be reduced when power-down mode is used while not  
converting. The part also features a power-down mode to  
maximize power efficiency at lower throughput rates.  
Current consumption is 1 μA maximum and 50 nA typically  
when in power-down mode.  
The conversion process and data acquisition are controlled  
CS  
using  
and the serial clock, allowing the devices to interface  
with microprocessors or DSPs. The input signal is sampled on  
the falling edge of  
point. There are no pipeline delays associated with the part.  
CS  
and the conversion is initiated at this  
The AD7910/AD7920 use advanced design techniques to  
achieve very low power dissipation at high throughput rates.  
4. Reference derived from the power supply.  
5. No pipeline delay. The parts feature a standard successive  
approximation ADC with accurate control of the sampling  
The reference for the part is taken internally from VDD. This  
allows the widest dynamic input range to the ADC. Thus, the  
analog input range for the part is 0 to VDD. The conversion rate  
is determined by the SCLK.  
CS  
instant via a  
input and once-off conversion control.  
1 Protected by U.S. Patent No. 6,681,332.  
Rev. C  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  
 

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