Low Power, 16-/24-Bit,
Sigma-Delta ADCs
AD7788/AD7789
FUNCTIONAL BLOCK DIAGRAM
FEATURES
REFIN(+) REFIN(–) GND
V
DD
AD7788: 16-bit resolution
AD7789: 24-bit resolution
Power
AD7788/
AD7789
CLOCK
Supply: 2.5 V to 5.25 V operation
Normal: 75 μA maximum
Power-down: 1 μA maximum
RMS noise: 1.5 μV
DOUT/RDY
DIN
AIN(+)
AIN(–)
SERIAL
INTERFACE
AND
CONTROL
LOGIC
Σ-Δ
ADC*
SCLK
CS
AD7788: 16-bit p-p resolution
AD7789: 19-bit p-p resolution (21.5 bits effective)
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator
*AD7788: 16-BIT ADC
AD7789: 24-BIT ADC
Figure 1.
GENERAL DESCRIPTION
VDD monitor channel
The AD7788/AD7789 are low power, low noise, analog front
ends for low frequency measurement applications. The AD7789
contains a low noise, 24-bit, ∑-Δ ADC with one differential
input. The AD7788 is a 16-bit version of the AD7789.
10-lead MSOP
INTERFACE
3-wire serial
The devices operate from an internal clock. Therefore, the
user does not have to supply a clock source to the devices.
The output data rate is 16.6 Hz, which gives simultaneous
50 Hz/60 Hz rejection.
SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible
Schmitt trigger on SCLK
APPLICATIONS
The parts operate with a single power supply from 2.5 V to
5.25 V. When operating from a 3 V supply, the power dissi-
pation for the part is 225 μW maximum. The AD7788/AD7789
are available in a 10-lead MSOP.
Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops
Rev. B
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