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AD7787_13

更新时间: 2024-09-13 12:52:31
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 307K
描述
Low Power, 2-Channel 24-Bit Sigma-Delta ADC

AD7787_13 数据手册

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Low Power, 2-Channel  
24-Bit Sigma-Delta ADC  
Data Sheet  
AD7787  
FEATURES  
APPLICATIONS  
Power  
Smart transmitters  
Battery applications  
Portable instrumentation  
Sensor measurement  
Temperature measurement  
Pressure measurement  
Weigh scales  
Supply: 2.5 V to 5.25 V operation  
Normal mode: 75 µA max  
Power-down mode: 1 µA max  
RMS noise: 1.1 µV at 9.5 Hz update rate  
19.5-bit p-p resolution (22 bits effective resolution)  
Integral nonlinearity: 3.5 ppm typical  
Simultaneous 50 Hz and 60 Hz rejection  
Internal clock oscillator  
4 to 20 mA loops  
GENERAL DESCRIPTION  
Rail-to-rail input buffer  
VDD monitor channel  
Temperature range: −40°C to +105°C  
10-lead MSOP  
The AD7787 is a low power, complete analog front end for low  
frequency measurement applications. It contains a low noise  
24-bit Σ-Δ ADC with one differential input and one single-  
ended input that can be buffered or unbuffered.  
INTERFACE  
The device operates from an internal clock. Therefore, the user  
does not have to supply a clock source to the device. The output  
data rate from the part is software programmable and can be  
varied from 9.5 Hz to 120 Hz, with the rms noise equal to  
1.1 µV at the lower update rate. The internal clock frequency  
can be divided by a factor of 2, 4, or 8, which leads to a  
3-wire serial  
SPI®, QSPI™, MICROWIRE™, and DSP compatible  
Schmitt trigger on SCLK  
reduction in the current consumption. The update rate, cutoff  
frequency, and settling time scales with the clock frequency.  
The part operates with a power supply from 2.5 V to 5.25 V.  
When operating from a 3 V supply, the power dissipation for  
the part is 225 µW maximum. It is housed in a 10-lead MSOP.  
FUNCTIONAL BLOCK DIAGRAM  
GND  
V
REFIN  
DD  
AD7787  
V
DD  
DOUT/RDY  
DIN  
SERIAL  
INTERFACE  
AND  
AIN1(+)  
SCLK  
CS  
Σ-∆  
ADC  
LOGIC  
BUF  
MUX  
CONTROL  
AIN1(–)  
AIN2  
CLOCK  
GND  
Figure 1.  
Rev. A  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  

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