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AD7768-1BCPZ-RL7 PDF预览

AD7768-1BCPZ-RL7

更新时间： 2024-11-11 20:39:47
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
76页 1573K
描述
DC to 204 kHz, Dynamic Signal Analysis, Precision 24-Bit ADC with Power Scaling

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AD7768-1BCPZ-RL7 数据手册

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DC to 204 kHz, Dynamic Signal Analysis,  
Precision 24-Bit ADC with Power Scaling  
AD7768-1  
Data Sheet  
Power supply  
FEATURES  
AVDD1 − AVSS = 5.0 V typical  
ADC for single-channel low power, platform DAQ designs  
Wide BW  
AVDD2 − AVSS = 2.0 V to 5.0 V typical  
Analog supplies can run from split supply (true bipolar)  
IOVDD − DGND = 1.8 V to 3.3 V typical  
Sinc filter BW range: DC to 204 kHz  
Low ripple FIR BW range: DC to 110.8 kHz  
Precision ac and dc performance  
108.5 dB dynamic range  
Low power mode can run from single 3.3 V supply  
Pin control or SPI interface configurable  
Suite of diagnostic check mechanisms  
−120 dB THD  
Temperature, interface CRC, and memory map CRC  
Package: 28-lead, 4 mm × 5 mm, LFCSP  
Temperature range: −40°C to +125°C  
1.1 ppm of FSR INL, 30 µV offset error, 30 ppm of FSR  
gain error  
Programmable ODR, filter type, and latency  
ODR values up to 1024 kSPS  
APPLICATIONS  
Linear phase digital filter options  
Low ripple FIR filter: 0.005 dB maximum pass-band  
ripple, dc to 102.4 kHz  
Platform ADC to serve a superset of measurements and  
sensor types  
Sound and vibration, acoustic, and material science  
research and development  
Control and hardware in loop verification  
Condition monitoring for predictive maintenance  
Electrical test and measurement  
Audio testing and current and voltage measurement  
Clinical EEG, EMG, and ECG vital signs monitoring  
USB-, PXI-, and Ethernet-based modular DAQ  
Channel to channel isolated modular DAQ designs  
Low latency sinc5 filter  
Low latency sinc3 filter enabling 50 Hz/60 Hz rejection  
Programmable power consumption and bandwidth  
Fast, highest speed  
52.224 kHz BW, 26.4 mW (sinc5 filter)  
110.8 kHz BW, 36.8 mW (FIR filter)  
Median, half speed: 55.4 kHz BW, 19.7 mW (FIR filter)  
Low power, low speed: 13.9 kHz BW, 6.75 mW (FIR filter)  
FUNCTIONAL BLOCK DIAGRAM  
AVDD1 REF+ REF–  
DGND  
AVDD2 REGCAPA REGCAPD IOVDD  
AD7768-1  
SYNC_IN  
1.8V  
LDO  
1.8V  
LDO  
SYNC_OUT  
÷2  
REFERENCE  
BUFFERS  
VCM  
RESET  
DRDY  
CS  
DOUT/RDY  
SDI  
SCLK  
WIDEBAND  
LOW RIPPLE  
FILTER  
ADC  
DATA  
SERIAL  
INTERFACE  
AIN+  
AIN–  
SINC5  
LOW LATENCY  
FILTER  
POWER  
SCALABLE  
Σ-Δ ADC  
SINC3 FILTER  
ENABLING  
50Hz/60Hz  
CONTROL  
BLOCK  
PRECHARGE  
BUFFERS  
REJECTION  
AVSS  
MCLK/XTAL2 XTAL1  
CLKSEL  
MODE3 TO MODE0  
(GPIO3 TO GPIO0)  
PIN/SPI  
Figure 1.  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2018 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
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