AD7721SQ

更新时间： 2024-09-16 22:49:59

品牌	Logo	应用领域
亚德诺 - ADI		转换器模数转换器
页数	文件大小	规格书
16页	262K
描述
CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC

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AD7721SQ 数据手册

CMOS 16-Bit,

468.75 kHz, Sigma-Delta ADC

AD7721

FUNCTIO NAL BLO CK D IAGRAM

FEATURES

16-Bit Sigm a-Delta ADC

468.75 kHz Output Word Rate (OWR)

No Missing Codes

Low -Pass Digital Filter

High Speed Serial Interface

Linear Phase

AGND

DGND

AD7721

DSUBST

REFIN

12-BIT A/D CONVERTER

VIN1

VIN2

⌺-⌬

MODULATOR

229.2 kHz Input Bandw idth

Pow er Supplies: AV_DD, DV_DD: +5 V ؎ 5%

Standby Mode (70 ␮W)

Parallel Mode (12-Bit/ 312.5 kHz OWR)

FIR

FILTER

DVAL/SYNC

CLK

DRDY

STBY/DB0

CAL/DB1

UNI/DB2

SDATA/DB11

RFS/DB10

CONTROL LOGIC

DB9

GENERAL D ESCRIP TIO N

T he AD7721 is a complete low power, 12-/16-bit, sigma-delta

ADC. T he part operates from a +5 V supply and accepts a

differential input of 0 V to 2.5 V or ±1.25 V. T he analog input

is continuously sampled by an analog modulator at twice the

clock frequency eliminating the need for external sample-and-

hold circuitry. T he modulator output is processed by two finite

impulse response (FIR) digital filters in series. T he on-chip

filtering reduces the external antialias requirements to first order

in most cases. Settling time for a step input is 97.07 µs while

the group delay for the filter is 48.53 µs when the master clock

equals 15 MHz.

DB6 SCLK/ DB8

DB7

DB3

DB4

SYNC/

DB5

Use of a single bit DAC in the modulator guarantees excellent

linearity and dc accuracy. Endpoint accuracy is ensured by on-

chip calibration of offset and gain. T his calibration procedure

minimizes the part’s zero-scale and full-scale errors.

T he output data is accessed from the output register through a

serial or parallel port. T his offers easy, high speed interfacing to

modern microcontrollers and digital signal processors. T he

serial interface operates in internal clocking (master) mode, the

AD7721 providing the serial clock.

T he AD7721 can be operated with input bandwidths up to

229.2 kHz. The corresponding output word rate is 468.75 kHz.

T he part can be operated with lower clock frequencies also.

T he sample rate, filter corner frequency and output word rate

will be reduced also, as these are proportional to the external

clock frequency. T he maximum clock frequencies in parallel

mode and serial mode are 10 MHz and 15 MHz respectively.

CMOS construction ensures low power dissipation while a

power-down mode reduces the power consumption to only

100 µW.

REV. A

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 781/ 329-4700

Fax: 781/ 326-8703

World Wide Web Site: http:/ / w w w .analog.com

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