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AD7680BRJZ-R2 PDF预览

AD7680BRJZ-R2

更新时间: 2024-10-28 12:26:39
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亚德诺 - ADI /
页数 文件大小 规格书
24页 301K
描述
3 mW, 100 kSPS, 16-Bit ADC in 6-Lead SOT-23

AD7680BRJZ-R2 数据手册

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3 mW, 100 kSPS,  
16-Bit ADC in 6-Lead SOT-23  
AD7680  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Fast throughput rate: 100 kSPS  
Specified for VDD of 2.5 V to 5.5 V  
Low power  
3 mW typ at 100 kSPS with 2.5 V supply  
3.9 mW typ at 100 kSPS with 3 V supply  
16.7 mW typ at 100 kSPS with 5 V supply  
Wide input bandwidth  
86 dB SNR at 10 kHz input frequency  
Flexible power/serial clock speed management  
No pipeline delays  
V
DD  
16-BIT SUCCESSIVE  
APPROXIMATION  
ADC  
V
T/H  
IN  
SCLK  
SDATA  
CS  
CONTROL  
LOGIC  
AD7680  
GND  
High speed serial interface  
SPI®/QSPI™/μWire/DSP compatible  
Standby mode: 0.5 μA max  
Figure 1.  
6-Lead SOT-23 and 8-Lead MSOP packages  
Table 1. MSOP/SOT-23 16-Bit PulSAR ADC  
APPLICATIONS  
Type/kSPS  
100 kSPS  
AD7684  
AD7683  
AD7680  
250 kSPS  
AD7687  
AD7685  
500 kSPS  
AD7688  
AD7686  
True Differential  
Pseudo Differential  
Unipolar  
Battery-powered systems:  
Personal digital assistants  
Medical instruments  
Mobile communications  
Instrumentation and control systems  
Remote data acquisition systems  
High speed modems  
Optical sensors  
GENERAL DESCRIPTION  
PRODUCT HIGHLIGHTS  
1. First 16-bit ADC in a SOT-23 package.  
The AD7680 is a 16-bit, fast, low power, successive  
approximation ADC. The part operates from a single 2.5 V to  
5.5 V power supply and features throughput rates up to 100 kSPS.  
The part contains a low noise, wide bandwidth track-and-hold  
amplifier that can handle input frequencies in excess of 7 MHz.  
2. High throughput with low power consumption.  
3. Flexible power/serial clock speed management. The  
conversion rate is determined by the serial clock, allowing  
the conversion time to be reduced through the serial clock  
speed increase. This allows the average power consumption  
to be reduced when a power-down mode is used while not  
converting. The part also features a shutdown mode to  
maximize power efficiency at lower throughput rates.  
Power consumption is 0.5 μA max when in shutdown.  
The conversion process and data acquisition are controlled  
CS  
using  
with microprocessors or DSPs. The input signal is sampled on  
CS  
and the serial clock, allowing the devices to interface  
the falling edge of  
and the conversion is also initiated at this  
point. There are no pipeline delays associated with the part.  
4. Reference derived from the power supply.  
5. No pipeline delays.  
The AD7680 uses advanced design techniques to achieve very  
low power dissipation at fast throughput rates. The reference for  
the part is taken internally from VDD, which allows the widest  
dynamic input range to the ADC. Thus, the analog input range  
for this part is 0 V to VDD. The conversion rate is determined by  
the SCLK frequency.  
This part features a standard successive approximation ADC  
with accurate control of the sampling instant via a  
once-off conversion control.  
CS  
input and  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.326.8703© 2004-2011 Analog Devices, Inc. All rights reserved.  

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