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AD75019JP PDF预览

AD75019JP

更新时间: 2024-11-14 22:09:23
品牌 Logo 应用领域
亚德诺 - ADI 开关
页数 文件大小 规格书
4页 75K
描述
16 x 16 Crosspoint Switch Array

AD75019JP 数据手册

 浏览型号AD75019JP的Datasheet PDF文件第2页浏览型号AD75019JP的Datasheet PDF文件第3页浏览型号AD75019JP的Datasheet PDF文件第4页 
16 
؋
 16 Crosspoint  
a
Switch Array  
AD75019  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
256 Switches in a 16 
؋
 16 Array  
Wide Signal Range: to Supply Rails of 24 V or ؎12 V  
Low On-Resistance: 200 Typ  
ANALOG  
INPUTS/OUTPUTS  
X0  
X15  
V
DD  
V
SS  
V
CC  
DGND  
TTL/CMOS/Microprocessor-Compatible Control Lines  
Serial Input Simplifies Interface  
+12V –12V +5V DGND  
SERIAL DATA IN  
Y0  
Serial Output Allows Cascading for More Channels  
Low Power Consumption: 2 mW Quiescent  
Compact 44-Lead PLCC  
SHIFT  
REGISTER  
CELL #256  
LATCH  
ANALOG  
SWITCH  
AD75019  
BUSED CLOCK  
LINES  
SERIAL  
DATA  
ANALOG  
OUTPUTS/  
INPUTS  
TO NEXT  
STAGES  
SERIAL  
DATA  
FROM  
PRIOR  
STAGES  
16 
؋
 16 ARRAY OF SWITCHES,  
LATCHES, AND SHIFT REGISTER  
CELLS (ONLY TWO LOCATIONS  
ARE SHOWN FOR CLARITY)  
BUSED CLOCK  
LINES  
Y15  
SHIFT  
REGISTER  
CELL #1  
ANALOG  
SWITCH  
LATCH  
PARALLEL  
CLOCK  
SERIAL  
CLOCK  
PCLK  
SCLK SOUT  
PRODUCT DESCRIPTION  
To extend the number of switches in the array, you may cascade  
multiple AD75019s. The SOUT output is the end of the shift  
register, and may be connected to the SIN input of the next  
AD75019.  
The AD75019 contains 256 analog switches in a 16 × 16 array.  
Any of the X or Y pins may serve as an input or output. Any or  
all of the X terminals may be programmed to connect to any or  
all of the Y terminals. The switches can accommodate signals  
with amplitudes up to the supply rails and have a typical on-  
resistance of 150 .  
The AD75019 is fabricated in Analog Devices’ BiMOS II  
process. This epitaxial BiCMOS process features CMOS  
devices for low distortion switches and bipolar devices for  
ESD protection.  
Data is loaded serially via the SIN input and clocked into an on-  
board 256-bit shift register via SCLK. When all the switch set-  
tings have been programmed, data is transferred into a set of  
256 latches via PCLK. The serial shift register is dynamic, so  
there is a minimum clock rate of 20 kHz. The maximum clock  
rate of 5 MHz allows loading times as short as 52 µs. The switch  
control latches are static and will hold their data as long as power  
is applied.  
REV. C  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 1999  

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