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AD7495ARZ

更新时间： 2024-11-15 12:33:15
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亚德诺 - ADI /
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24页 453K
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1 MSPS,12-Bit ADCs

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AD7495ARZ 数据手册

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1 MSPS,12-Bit ADCs  
AD7475/AD7495  
FUNCTIONAL BLOCK DIAGRAMS  
FEATURES AND APPLICATIONS  
Fast throughput rate: 1 MSPS  
V
DD  
Specified for VDD of 2.7 V to 5.25 V  
12-BIT  
SUCCESSIVE  
APPROXIMATION  
ADC  
Low power:  
T/H  
V
IN  
4.5 mW max at 1 MSPS with 3 V supplies  
10.5 mW max at 1 MSPS with 5 V supplies  
Wide input bandwidth:  
REF IN  
SCLK  
SDATA  
CS  
68 dB SNR at 300 kHz input frequency  
Flexible power/serial clock speed management  
No pipeline delays  
CONTROL  
LOGIC  
V
DRIVE  
High speed serial interface:  
AD7475  
SPI™-/QSPI™-/MICROWIRE™-/DSP-compatible  
On-board reference: 2.5 V (AD7495 only)  
Standby mode: 1 μA max  
GND  
V
DD  
8-lead MSOP and SOIC packages  
12-BIT  
SUCCESSIVE  
APPROXIMATION  
ADC  
T/H  
V
IN  
Battery-powered systems  
Personal digital assistants  
Medical instruments  
Mobile communications  
Instrumentation and control systems  
Data acquisition systems  
Optical sensors  
REF OUT  
BUF  
2.5V  
SCLK  
SDATA  
CS  
CONTROL  
LOGIC  
REFERENCE  
V
DRIVE  
AD7495  
GND  
GENERAL DESCRIPTION  
Figure 1.  
The AD7475/AD74951 are 12-bit, high speed, low power,  
successive-approximation ADCs that operate from a single  
2.7 V to 5.25 V power supply with throughput rates up to  
1 MSPS. They contain a low noise, wide bandwidth track-and-  
hold amplifier that can handle input frequencies above 1 MHz.  
PRODUCT HIGHLIGHTS  
1. The AD7475 offers 1 MSPS throughput rates with 4.5 mW  
power consumption.  
2. Single-supply operation with VDRIVE function. The  
AD7475/AD7495 operate from a single 2.7 V to 5.25 V  
supply. The VDRIVE function allows the serial interface  
to connect directly to either 3 V or 5 V processor systems  
The conversion process and data acquisition are controlled  
using  
and the serial clock, allowing the devices to interface  
CS  
with microprocessors or DSPs. The input signal is sampled on  
the falling edge of and conversion is initiated at this point.  
CS  
independent of VDD  
.
The conversion time is determined by the SCLK frequency.  
There are no pipeline delays associated with the part.  
3. Flexible power/serial clock speed management. The con-  
version rate is determined by the serial clock, allowing the  
conversion time to be reduced through the serial clock  
speed increase. The parts also feature shutdown modes to  
maximize power efficiency at lower throughput rates. This  
allows the average power consumption to be reduced while  
not converting. Power consumption is 1 μA when in full  
shutdown.  
The AD7475/AD7495 use advanced design techniques to  
achieve very low power dissipation at high throughput rates.  
With 3 V supplies and a 1 MSPS throughput rate, the AD7475  
consumes just 1.5 mA, while the AD7495 consumes 2 mA.  
With 5 V supplies and 1 MSPS, the current consumption is  
2.1 mA for the AD7475 and 2.6 mA for the AD7495.  
4. No pipeline delay. The parts feature a standard successive  
approximation ADC with accurate control of the sampling  
The analog input range for the parts is 0 V to REF IN. The 2.5 V  
reference for the AD7475 is applied externally to the REF IN  
pin, while the AD7495 has an on-board 2.5 V reference.  
instant via a  
input and once-off conversion control.  
CS  
1Protected by U.S. Patent No. 6,681,332  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  
 
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AD7495ARZ 替代型号

型号 品牌 替代类型 描述 数据表
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