1.25 MSPS, 16 mW Internal REF and CLK,
12-Bit Parallel ADC
a
AD7492
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Specified for VDD of 2.7 V to 5.25 V
Throughput Rate of 1 MSPS—AD7492
Throughput Rate of 1.25 MSPS—AD7492-5
Low Power
4 mW Typ at 1 MSPS with 3 V Supplies
11 mW Typ at 1 MSPS with 5 V Supplies
Wide Input Bandwidth
AVDD
VDRIVE
DVDD
REF OUT
2.5V
REF
CLOCK
OSCILLATOR
BUF
DB11
DB0
70 dB Typ SNR at 100 kHz Input Frequency
2.5 V Internal Reference
OUTPUT
DRIVERS
T/H
12-BIT SAR
ADC
VIN
On-Chip CLK Oscillator
Flexible Power/Throughput Rate Management
No Pipeline Delays
High-Speed Parallel Interface
Sleep Mode: 50 nA Typ
24-Lead SOIC and TSSOP Packages
PS/FS
CONTROL
LOGIC
CONVST
CS
RD
AD7492
BUSY
GENERAL DESCRIPTION
The AD7492 and AD7492-5 are 12-bit high-speed, low power,
successive-approximation ADCs. The parts operate from a
single 2.7 V to 5.25 V power supply and feature throughput rates
up to 1.25 MSPS. They contain a low-noise, wide bandwidth
track/hold amplifier that can handle bandwidths up to 10 MHz.
AGND
DGND
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption
The AD7492-5 offers 1.25 MSPS throughput with 16 mW
power consumption.
The conversion process and data acquisition are controlled using
standard control inputs allowing easy interface to microproces-
sors or DSPs. The input signal is sampled on the falling edge of
CONVST and conversion is also initiated at this point. The
BUSY goes high at the start of conversion and goes low 880 ns
(AD7492) or 680 ns (AD7492-5) later to indicate that the con-
version is complete. There are no pipeline delays associated with
the part. The conversion result is accessed via standard CS and
RD signals over a high-speed parallel interface.
2. Flexible Power/Throughput Rate Management
The conversion time is determined by an internal clock. The
part also features two sleep modes, partial and full, to maxi-
mize power efficiency at lower throughput rates.
3. No Pipeline Delay
The part features a standard successive-approximation ADC
with accurate control of the sampling instant via a CONVST
input and once-off conversion control.
The AD7492 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. With 5 V
supplies and 1.25 MSPS, the average current consumption
AD7492-5 is typically 2.75 mA. The part also offers flexible
power/throughput rate management.
4. Flexible Digital Interface
The VDRIVE feature controls the voltage levels on the I/O
digital pins.
5. Fewer Peripheral Components
It is also possible to operate the part in a full sleep mode and a
partial sleep mode, where the part wakes up to do a conversion
and automatically enters a sleep mode at the end of conversion.
The type of sleep mode is hardware selected by the PS/FS pin.
Using these sleep modes allows very low power dissipation num-
bers at lower throughput rates.
The AD7492 optimizes PCB space by using an internal
Reference and internal CLK.
The analog input range for the part is 0 to REF IN. The 2.5 V
reference is supplied internally and is available for external refer-
encing. The conversion rate is determined by the internal clock.
REV. 0
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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
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© Analog Devices, Inc., 2001