Pseudo Differential Input, 1 MSPS,
10-/12-Bit ADCs in an 8-Lead SOT-23
AD7441/AD7451
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
Fast throughput rate: 1 MSPS
DD
Specified for VDD of 2.7 V to 5.25 V
Low power at maximum throughput rate:
4 mW maximum at 1 MSPS with VDD = 3 V
9.25 mW maximum at 1 MSPS with VDD = 5 V
Pseudo differential analog input
Wide input bandwidth:
V
V
IN+
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
IN–
V
REF
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
SCLK
High speed serial interface:
SDATA
AD7441/AD7451
CONTROL LOGIC
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Power-down mode: 1 μA maximum
8-lead SOT-23 and MSOP packages
CS
APPLICATIONS
GND
Figure 1.
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
1. Operation with 2.7 V to 5.25 V Power Supplies.
The AD7441/AD74511 are, respectively, 10-/12-bit high speed,
low power, single-supply, successive approximation (SAR),
analog-to-digital converters (ADCs) that feature a pseudo
differential analog input. These parts operate from a single
2.7 V to 5.25 V power supply and achieve very low power
dissipation at high throughput rates of up to 1 MSPS.
2. High Throughput with Low Power Consumption.
With a 3 V supply, the AD7441/AD7451 offer 4 mW maxi-
mum power consumption for a 1 MSPS throughput rate.
3. Pseudo Differential Analog Input.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. These
parts also feature a shutdown mode to maximize power
efficiency at lower throughput rates.
The AD7441/AD7451 contain a low noise, wide bandwidth,
differential track-and-hold (T/H) amplifier that handles input
frequencies up to 3.5 MHz. The reference voltage for these
devices is applied externally to the VREF pin and can range from
100 mV to VDD, depending on the power supply and what suits
the application.
5. Variable Voltage Reference Input.
6. No Pipeline Delays.
The conversion process and data acquisition are controlled
CS
using
with microprocessors or DSPs. The input signals are sampled
CS
and the serial clock, allowing the device to interface
CS
7. Accurate Control of Sampling Instant via
Once-Off Conversion Control.
Input and
on the falling edge of
The SAR architecture of these parts ensures that there are no
pipeline delays.
when the conversion is initiated.
8. ENOB > 10 Bits Typically with 500 mV Reference.
1 Protected by U.S. Patent Number 6,681,332.
Rev. D
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