Differential Input, 1 MSPS
a
12-Bit ADC in ꢀSOIC-8 and SO-8
AD7450
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fast Throughput Rate: 1 MSPS
Specified for VDD of 3 V and 5 V
Low Power at Max Throughput Rate:
3.75 mW Max at 833 kSPS with 3 V Supplies
9 mW Max at 1 MSPS with 5 V Supplies
Fully Differential Analog Input
Wide Input Bandwidth:
V
DD
V
IN+
12-BIT SUCCESSIVE
APPROXIMATION
ADC
T/H
V
IN–
70 dB SINAD at 300 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
V
REF
High-Speed Serial Interface—SPITM/QSPITM
MICROWIRETM/DSP Compatible
Power-Down Mode: 1 ꢀA Max
8-Lead ꢀSOIC and SOIC Packages
SCLK
SDATA
CS
AD7450
CONTROL
LOGIC
APPLICATIONS
Transducer Interface
Battery-Powered Systems
Data Acquisition Systems
Portable Instrumentation
Motor Control
GND
Communications
GENERAL DESCRIPTION
The AD7450 is a 12-bit, high-speed, low power, successive
approximation (SAR) analog-to-digital converter that features a
fully differential analog input. It operates from a single 3 V or 5 V
power supply and features throughput rates up to 833 kSPS or
1 MSPS, respectively.
The AD7450 uses advanced design techniques to achieve low
power dissipation at high throughput rates.
PRODUCT HIGHLIGHTS
1. Operation with either 3 V or 5 V power supplies.
This part contains a low noise, wide bandwidth, differential track
and-hold amplifier (T/H) that can handle input frequencies in
excess of 1 MHz with the –3 dB point typically being 20 MHz.
-
2. High throughput with low power consumption. With a 3 V
supply, the AD7450 offers 3.75 mW max power consumption
for 833 kSPS throughput.
The reference voltage for the AD7450 is applied externally to the
VREF pin and can be varied from 100 mV to 3.5 V, depending
on the power supply and what suits the application. The value of
the reference voltage determines the common-mode voltage
range of the part. With this truly differential input structure and
variable reference input, the user can select a variety of input
ranges and bias points.
3. Fully differential analog input.
4. Flexible power/serial clock speed management. The conversion
rate is determined by the serial clock, allowing the power
to be reduced as the conversion time is reduced through
the serial clock speed increase. This part also features a
shutdown mode to maximize power efficiency at lower
throughput rates.
The conversion and data acquisition processes are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled
on the falling edge of CS, and the conversion is also initiated at
this point.
5. Variable voltage reference input.
6. No pipeline delay.
7. Accurate control of the sampling instant via a CS input and
once-off conversion control.
The SAR architecture of this part ensures that there are no
pipeline delays.
8. ENOB > 8 bits typically with 100 mV reference.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
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reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
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Tel: 781/329-4700
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© Analog Devices, Inc., 2002