80 MHz Bandwidth, IF Receiver
Data Sheet
AD6677
FEATURES
GENERAL DESCRIPTION
JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
Signal-to-noise ratio (SNR) = 71.9 dBFS at 185 MHz AIN and
250 MSPS with noise shaping requantizer (NSR) set to 33%
Spurious-free dynamic range (SFDR) = 87 dBc at 185 MHz AIN
and 250 MSPS
Total power consumption: 435 mW at 250 MSPS
1.8 V supply voltages
Integer 1 to 8 input clock divider
The AD6677 is an 11-bit, 250 MSPS, intermediate frequency
(IF) receiver specifically designed to support multi-antenna
systems in telecommunication applications where high dynamic
range performance, low power, and small size are desired.
The device consists of a high performance ADC and an NSR
digital block. The ADC consists of a multistage, differential
pipelined architecture with integrated output error correction
logic, and each ADC features a wide bandwidth switched capacitor
sampling network within the first stage of the differential pipeline.
An integrated voltage reference eases design considerations. A duty
cycle stabilizer compensates for variations in the ADC clock duty
cycle, allowing the converters to maintain excellent performance.
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal analog-to-digital converter (ADC) voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer (DCS)
Serial port control
The ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance
in a smaller frequency band within the Nyquist bandwidth.
The device supports two different output modes selectable via
the serial port interface (SPI). With the NSR feature enabled,
the output of the ADC is processed such that the AD6677
supports enhanced SNR performance within a limited portion
of the Nyquist bandwidth while maintaining an 11-bit output
resolution.
Energy saving power-down modes
APPLICATIONS
Communications
Diversity radio and smart antenna multiple input, multiple
output (MIMO) systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
General-purpose software radios
FUNCTIONAL BLOCK DIAGRAM
AVDD DRVDD DVDD
AGND DGND DRGND
AD6677
JESD204B
INTERFACE
NOISE
SHAPING
REQUANTIZER
(NSR)
VIN+
VIN–
VCM
CML, TX
OUTPUTS
SERDOUT0±
PIPELINE
11-BIT ADC
HIGH
SPEED
SERIALIZERS
CMOS
DIGITAL
INPUT
CONTROL
REGISTERS
PDWN
SYSREF±
SYNCINB±
CLK±
CLOCK
GENERATION
RFCLK
CMOS
DIGITAL
OUTPUT
FAST
DETECT
CMOS DIGITAL
INPUT/OUTPUT
FD
SDIO SCLK CS
RST
Figure 1.
Rev. C
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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