Datasheet > AD6676BCBZRL

AD6676BCBZRL

更新时间： 2024-01-05 10:29:48

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
90页	1931K
描述
Wideband IF Receiver Subsystem

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AD6676BCBZRL 数据手册

Wideband IF Receiver Subsystem

Data Sheet

AD6676

FEATURES

APPLICATIONS

High instantaneous dynamic range

Noise figure (NF) as low as 13 dB

Wideband cellular infrastructure equipment and repeaters

Point-to-point microwave equipment

Instrumentation

Spectrum and communication analyzers

Software defined radio

Noise spectral density (NSD) as low as −159 dBFS/Hz

IIP3 up to 36.9 dBm with spurious tones <−99 dBFS

Tunable band-pass Σ-Δ analog-to-digital converter (ADC)

20 MHz to 160 MHz signal bandwidth

70 MHz to 450 MHz IF center frequency

Configurable input full-scale level of −2 dBm to −14 dBm

Easy to drive resistive IF input

Gain flatness of 1 dB with under 0.5 dB out-of-band peaking

Alias rejection greater than 50 dB

2.0 GSPS to 3.2 GSPS ADC clock rate

GENERAL DESCRIPTION

The AD6676¹is a highly integrated IF subsystem that can

digitize radio frequency (RF) bands up to 160 MHz in width

centered on an intermediate frequency (IF) of 70 MHz to

450 MHz. Unlike traditional Nyquist IF sampling ADCs, the

AD6676 relies on a tunable band-pass Σ-Δ ADC with a high

oversampling ratio to eliminate the need for band specific IF

SAW filters and gain stages, resulting in significant simplification of

the wideband radio receiver architecture. On-chip quadrature

digital downconversion followed by selectable decimation filters

reduces the complex data rate to a manageable rate between

62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is

transferred to the host via a single or dual lane JESD204B interface

supporting line rates of up to 5.333 Gbps.

On-chip PLL clock multiplier

16-bit I/Q rate up to 266 MSPS

On-chip digital signal processing

NCO and quadrature digital downconverter (QDDC)

Selectable decimation factor of 12, 16, 24, and 32

Automatic gain control (AGC) support

On-chip attenuator with 27 dB span in 1 dB steps

Fast attenuator control via configurable AGC data port

Peak detection flags with programmable thresholds

Single or dual lane, JESD204B capable

Low power consumption: 1.20 W

1.1 V and 2.5 V supply voltage

TDD power saving up to 60%

4.3 mm × 5.0 mm WLCSP

FUNCTIONAL BLOCK DIAGRAM

AGC4, AGC3

AGC2, AGC1

VSS2IN

VSS2OUT VDD2NV

VDDIO RESETB

–2.0V

REG

CSB

AGC

SUPPORT

SCLK

SDIO

SDO

SPI

27dB ATTENUATOR

(1dB STEPS)

VDDHSI

QDDC +

NCO

VIN+

VIN–

BAND-PASS

Σ-∆ ADC

SERDOUT0+

SERDOUT0–

SERDOUT1+

SERDOUT1–

M = 12,

16, 24,

L+

L–

JESD204B

SUBCLASS 1

CONTROL

SYNCINB±

SYSREF±

CLOCK

GENERATION

CLOCK

SYNTHESIZER

AD6676

VDD2 VDDL VDD1

VSSA VDDD VSSD

VDDQ VDDC

CLK+ CLK–

Figure 1.

¹This product is protected by U.S. and international patents.

Rev. D Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

12 3 4 5 6 7...90

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与AD6676BCBZRL相关器件

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AD667-703D	ADI	获取价格	12-BIT DAC
AD667-703F	ADI	获取价格	12-BIT DAC
AD667-713F	ADI	获取价格	12-BIT DAC
AD6677BCPZ	ADI	获取价格	80 MHz Bandwidth, IF Receiver
AD6677BCPZRL7	ADI	获取价格	80 MHz Bandwidth, IF Receiver
AD6677EBZ	ADI	获取价格	80 MHz Bandwidth, IF Receiver
AD667883B	ADI	获取价格	Microprocessor-Compatible 12-Bit D/A Converter
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