Datasheet > AD6672

AD6672

更新时间： 2024-02-05 20:21:41

品牌	Logo	应用领域
亚德诺 - ADI		接收机
页数	文件大小	规格书
32页	1474K
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IF Receiver

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数据手册

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AD6672 数据手册

IF Receiver

AD6672

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

AGND

DRVDD

Performance with NSR enabled

SNR: 75.2 dBFS in a 55 MHz band to 185 MHz at 250 MSPS

SNR: 72.8 dBFS in an 82 MHz band to 185 MHz at 250 MSPS

Performance with NSR disabled

SNR: 66.4 dBFS up to 185 MHz at 250 MSPS

SFDR: 87 dBc up to 185 MHz at 250 MSPS

Total power consumption: 358 mW at 250 MSPS

1.8 V supply voltages

LVDS (ANSI-644 levels) outputs

Integer 1-to-8 input clock divider (625 MHz maximum input)

Internal ADC voltage reference

DCO±

0/D0±

VIN+

VIN–

VCM

PIPELINE

ADC

NOISE SHAPING

REQUANTIZER

AD6672

D9±/D10±

OR±

REFERENCE

1-TO-8

CLOCK

DIVIDER

SERIAL PORT

Flexible analog input range

SCLK

SDIO

CSB

CLK+ CLK–

1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)

Differential analog inputs with 350 MHz bandwidth

Serial port control

Figure 1.

Energy saving power-down modes

User-configurable, built-in self test (BIST) capability

APPLICATIONS

Communications

Diversity radio and smart antenna (MIMO) systems

Multimode digital receivers (3G)

WCDMA, LTE, CDMA2000

WiMAX, TD-SCDMA

I/Q demodulation systems

General-purpose software radios

The ADC core output is connected internally to a noise shaping

requantizer (NSR) block. The device supports two output modes

that are selectable via the serial port interface (SPI). With the

NSR feature enabled, the outputs of the ADCs are processed such

that the AD6672 supports enhanced SNR performance within a

limited region of the Nyquist bandwidth while maintaining an

11-bit output resolution. The NSR block is programmed to provide

a bandwidth of up to 33% of the sample clock. For example, with

a sample clock rate of 250 MSPS, the AD6672 can achieve up to

73.6 dBFS SNR for an 82 MHz bandwidth at 185 MHz f_IN.

GENERAL DESCRIPTION

The AD6672 is an 11-bit intermediate receiver with sampling

speeds of up to 250 MSPS. The AD6672 is designed to support

communications applications, where low cost, small size, wide

bandwidth, and versatility are desired.

The ADC core features a multistage, differential pipelined

architecture with integrated output error correction logic. The

ADC features wide bandwidth inputs supporting a variety of

user-selectable input ranges. An integrated voltage reference

eases design considerations. A duty cycle stabilizer is provided

to compensate for variations in the ADC clock duty cycle,

allowing the converters to maintain excellent performance.

With the NSR block disabled, the ADC data is provided directly

to the output with an output resolution of 11 bits. The AD6672

can achieve up to 66.6 dBFS SNR for the entire Nyquist bandwidth

when operated in this mode.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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