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AD5582YRU-REEL7 PDF预览

AD5582YRU-REEL7

更新时间: 2024-11-27 22:09:03
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
8页 161K
描述
QUAD, Parallel-Input, Voltage Output, 12-/10-Bit Digital-to-Analog Converter

AD5582YRU-REEL7 数据手册

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PRELIMINARY TECHNICAL DATA  
QUAD, Parallel-Input, Voltage Output,  
a
12-/10-Bit Digital-to-Analog Converter  
AD5582/AD5583  
FEATURES  
FUNCTIONAL DIAGRAM  
12-Bit Linearity and Monotonic –40oC to +125oC  
Single +5V to +12V or dual 5V supply  
Unipolar or Bipolar Operation  
Double Buffered Registers Enable Simultaneous Multi-  
Channels Update  
V
V
V
V
V
RLA RHA RLB RHB  
DD  
3
2
4
5
1
A1  
A0  
37  
ADDR  
DECODE  
36  
24  
6
V
V
OA  
OB  
4 Separate Rail-to Rail Reference Inputs  
Parallel Interface  
Data Readback Capability  
DB11  
DB10 25  
I
N
T
E
R
F
A
C
E
7
26  
DB9  
27  
DB8  
Do  
5µs Settling Time  
28  
38  
39  
DB7  
RA  
RB  
DAC  
REG  
IN  
Di  
20k  
20kΩ  
29  
DB6  
REG  
APPLICATIONS  
30  
DB5  
Process Control Equipment  
Closed Loop Servo Control  
Data Acquisition Systems  
Digitally Controlled Calibration  
Motor Control  
31  
DB4  
40 RC  
32  
DB3  
33  
AD5582  
DB2  
34  
DB1  
8
AGND  
OE  
35  
DB0  
Optical Network Control Loops  
23  
CS  
V
9
OC  
GENERAL DESCRIPTION  
22  
W/R  
CONTROL  
LOGIC  
V
V
10  
19  
LOGIC  
OD  
The AD5582/AD5583 family of quad, 12-/10-bit, voltage-output  
digital-to-analog converter is designed to operate from a single +5  
to +15 volt or a dual 5V supply. Built using a CBCMOS process,  
this monolithic DAC offers the user low cost, and ease-of-use in  
single or dual-supply systems.  
17  
MSB  
18  
21  
RS  
LDAC  
16  
12  
11  
20  
14  
13  
15  
V
V
V
V
V
RLC SS  
RHC  
DGND  
RLD  
RHD  
DVDD  
The applied external reference VREF determines the full-scale  
output voltage. Valid VREF values include VSS<VREF<VDD resulting  
in a wide selection of full scale outputs. For multiplying  
applications AC inputs can be as large as |VDD-VSS|. Two on-board  
precision trimmed resistors are available for 4-Quadrant  
configurations.  
+2.5V  
VREFH  
AD5582  
DAC A  
ADR421  
A
B
C
D
2.5V  
2.5V  
A doubled-buffered parallel interface offers 25Mbps data load rates.  
A common level-sensitive load-DAC strobe (LDAC) input allows  
simultaneous update of all DAC outputs from previously loaded  
Input Registers. An external asynchronous reset (RS) forces all  
registers to the zero code state when MSB='0' or to midscale when  
MSB='1'.  
RA  
DAC B  
DAC C  
DAC D  
RC  
RB  
VREFL  
2.5V  
2.5V  
A
B
C
D
-2.5V  
Both parts are offered in the same pin-out to allow users to select  
the amount of resolution appropriate for their application without  
circuit card redesign.  
The AD5582/AD5583 are specified over the extended industrial  
(-40°C to +125°C) temperature range. Packages available include  
thin 1.1 mm TSSOP-48 package.  
DIG ITAL CIRCUITRY O MITTED FO R CLARITY  
Figure 1 Using Onboard Offset resistors to generate a negative  
voltage REF  
REV PrC, 23 APR '01  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Information furnished by Analog Devices is believed to be accurate and reliable. However,  
no responsibility is assumed by Analog Devices for its use; nor for any infringements of  
patents or other rights of third parties which may result from its use. No license is granted  
by implication or otherwise under any patent or patent rights of Analog Devices.  
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com  
Fax:781/326-8703  
©Analog Devices, Inc., 2000  

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