Dual 8-/10-/12-Bit, High Bandwidth,
Multiplying DACs with Serial Interface
Data Sheet
AD5429/AD5439/AD5449
FEATURES
GENERAL DESCRIPTION
The AD5429/AD5439/AD54491 are CMOS, 8-, 10-, and 12-bit,
dual-channel, current output digital-to-analog converters (DAC),
respectively. These devices operate from a 2.5 V to 5.5 V power
supply, making them suited to battery-powered and other
applications.
10 MHz multiplying bandwidth
INL of 0.25 LSB @ 8 bits
16-lead TSSOP package
2.5 V to 5.5 V supply operation
10 V reference input
50 MHz serial interface
As a result of being manufactured on a CMOS submicron process,
these parts offer excellent 4-quadrant multiplication character-
istics, with large signal multiplying bandwidths of 10 MHz.
2.47 MSPS update rate
Extended temperature range: −40°C to +125°C
4-quadrant multiplication
Power-on reset
0.5 µA typical current consumption
Guaranteed monotonic
Daisy-chain mode
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier.
Readback function
APPLICATIONS
Portable battery-powered applications
Waveform generators
These DACs use a double-buffered, 3-wire serial interface that
is compatible with SPI, QSPI™, MICROWIRE™, and most DSP
interface standards. In addition, a serial data out (SDO) pin allows
daisy-chaining when multiple packages are used. Data readback
allows the user to read the contents of the DAC register via the
SDO pin. On power-up, the internal shift register and latches
are filled with 0s, and the DAC outputs are at zero scale.
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
The AD5429/AD5439/AD5449 DACs are available in 16-lead
TSSOP packages. The EV-AD5415/49SDZ evaluation board is
available for evaluating DAC performance. For more
Ultrasound
Gain, offset, and voltage trimming
information, see the UG-297 evaluation board user guide.
FUNCTIONAL BLOCK DIAGRAM
V
A
REF
RFB
R
AD5429/AD5439/AD5449
V
DD
R
A
FB
SYNC
I
1A
OUT
OUT
SHIFT
REGISTER
INPUT
REGISTER
DAC
REGISTER
8-/10-/12-BIT
R-2R DAC A
SCLK
SDIN
I
2A
SDO
CLR
LDAC
I
I
1B
2B
OUT
INPUT
REGISTER
DAC
REGISTER
8-/10-/12-BIT
R-2R DAC B
POWER-ON
RESET
OUT
R
B
FB
RFB
R
LDAC
V
B
REF
Figure 1.
1 U.S. Patent Number 5,689,257.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com