PRELIMINARY TECHNICAL DATA
40-Channel,3V/5VSingleSupply,
a
Preliminary Technical Data
14-Bit,Voltage-OutputDAC
AD5380
FEATURES
GENERAL DESCRIPTION
Guaranteed Monotonic
INL Error: 4LSB max
The AD5380 is a complete single supply, 40-channel, 14-
bit DAC available in 100-lead LQFP package. All
40-channels have an on-chip output amplifier with rail-to-
rail operation. The AD5380 includes an internal 1.25/
2.5V, 10ppm/°C reference, an on-chip channel monitor
function that multiplexes the analog outputs to a common
MON_OUT pin for external monitoring and an output
amplifier boost mode that allows the amplifier settling
time to be optimized. The AD5380 contains a double
buffered parallel interface featuring a WR pulse width of
On-Chip 1.25/2.5V, 10ppm/°C Reference
Temperature Range: -40°C to +85°C
Rail to Rail Output Amplifier
Package Type: 100-lead LQFP (14mm x 14mm)
User Interfaces:
Parallel,
Serial (SPI, QSPI, Microwire and DSP compatible
featuring Data Readback)
I2C Compatible Interface
20ns, a serial interface compatible with SPITM, QSPITM
MICROWIRETM and DSP interface standards with
interface speeds in excess of 30MHz and an I2C
,
INTEGRATED FUNCTIONS
Channel Monitor
Simultaneous Output Update via LDAC
Clear Function to User Programmable Code
Amplifier Boost Mode to Optimize Slew Rate
User Programmable Offset and Gain Adjust
Toggle Mode: Enables Squarewave Generation
compatible interface supporting 400kHz data transfer rate.
An input register followed by a DAC register provides
double buffering allowing the DAC outputs to be updated
independantly or simultaneously using the LDAC input.
Each channel has a programmable gain and offset adjust
register allowing the user to fully calibrate any DAC Channel.
Power consumption is typically 0.3mA/channel.
APPLICATIONS
Variable Optical Attenuators (VOA)
Level Setting
Optical Microelectromechanical Systems (MEMs)
Control Systems
FUNCTIONAL BLOCK DIAGRAM
DVDD (X3)
AVDD (X5) AGND (X5)
DAC GND (X5)
DGND (X3)
REFGND
REFOUT/ REFIN SIGNAL GND (X5)
PD
2.5V
Reference
SER/PAR
FIFO EN
AD5380
CS/(SYNC/AD0)
WR/(DCEN/AD1)
SDO(A/B)
INPUT
REG
0
14
14
DAC
REG
0
14
14
X
+
DAC 0
+
VOUT 0
14
14
m REG0
c REG0
-
DB13 /(DIN/SDA)
DB12 /(SCLK/SCL)
FIFO
+
STATE
MACHINE
+
CONTROL
LOGIC
R
DB11 /(SPI/I2C)
R
DB10
.
DB0
INTERFACE
CONTROL
LOGIC
14
INPUT
REG
1
14
14
DAC
REG
14
X
14
A5
A0
DAC 1
+
+
-
1
VOUT 1
.
.
.
.
14
m REG1
.
.
.
.
VOUT 2
VOUT 3
.
.
.
14
c REG1
R
REG0
REG1
.
.
.
.
.
.
.
.
R
.
.
VOUT 4
VOUT 5
VOUT 6
POWER-ON
RESET
INPUT
REG
6
14
RESET
BUSY
CLR
DAC
REG
6
14
14
14
DAC 6
X
+
+
-
14
14
m REG6
c REG6
R
R
14
14 INPUT
VOUT 0 .......... VOUT 38
DAC
REG
7
14
X
REG
7
+
+
-
DAC 7
VOUT 7
VOUT 8
14
14
m REG7
c REG7
39 -TO-1
MUX
R
R
X5
VOUT 38
VOUT 39 / MON_OUT
LDAC
*Protected by U.S. Patent Nos. 5,969,657; other patents pending.
SPI and QSPI are Trademarks of Motorola, Inc.
MICROWIRE is a Trademark of National Semiconductor Corporation.
REV. PrF 09/2003
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
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© Analog Devices, Inc., 2003