Datasheet > AD5311BRTZ-500RL71

AD5311BRTZ-500RL71

更新时间： 2022-04-12 13:54:53

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	429K
描述
2.5 V to 5.5 V, 120 Î¼A, 2-Wire Interface, Voltage-Output 8-/10-/12-Bit DACs

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AD5311BRTZ-500RL71 数据手册

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AD5301/AD5311/AD5321

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND

SDA

SCL

AD5301/

AD5311/

AD5321

GND

SDA

SCL

AD5301/

AD5311/

AD5321

TOP VIEW

(Not to Scale)

OUT

(Not to Scale)

OUT

Figure 3. 8-Lead MSOP

(RM-8) Pin Configuration

Figure 4. 6-Lead SOT-23

(RJ-6) Pin Configuration

Table 5. Pin Function Descriptions

MSOP SOT-23

Pin No. Pin No. Mnemonic Description

ꢀ

V_DD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled

with a 10 μF in parallel with a 0.1 μF capacitor to GND.

Address Input. Sets the least significant bit of the 7-bit slave address.

N/A

Address Input. Sets the second least significant bit of the 7-bit slave address.

Buffered Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.

V_OUT

N/A

Active Low Control Input. Acts as a hardware power-down option. This pin overrides any software

power-down option. The DAC output goes three-state and the current consumption of the part

drops to 50 nA @ 3 V (200 nA @ 5 V).

ꢀ

SCL

Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 1ꢀ-bit input shift

be CMOS/TTL driven.

Serial Data Line. This is used in conjunction with the SCL line to clock data into the 1ꢀ-bit input shift

two bytes for the AD5311/AD5321) during the read cycle. It is a bidirectional open-drain data line that

should be pulled to the supply with an external pull-up resistor. If not used in readback mode, SDA may

be CMOS/TTL driven.

SDA

GND

Ground Reference Point for All Circuitry on the Part.

Rev. B | Page 7 of 24

1...4 5 678 9 10...24

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